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TDA4850 Datasheet(PDF) 6 Page - NXP Semiconductors

Part No. TDA4850
Description  Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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 6 page
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1997 Jun 05
6
Philips Semiconductors
Product specification
Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors
TDA4850
Horizontal driver
This open-collector output stage (pin 3) can directly drive
an external driver transistor. The saturation voltage is
300 mV at 20 mA. To protect the line deflection transistor,
the horizontal output stage does not conduct at VP < 6.4 V
(pin 1).
Vertical oscillator and amplitude control
This stage is designed for fast stabilization of the vertical
amplitude after changes in sync conditions.
The free-running frequency fo is determined by the values
of RVOS and CVOS. The recommended values should be
altered marginally only to preserve the excellent linearity
and noise performance. The vertical drive currents I5 and
I6 are in relation to the value of RVOS. Therefore, the
oscillator frequency must be determined only by CVOS on
pin 16.
f
o
1
10.8
R
VOS
×
C
VOS
×
----------------------------------------------------
=
To achieve a stabilized amplitude the free-running
frequency fo (without adjustment) must be lower than the
lowest occurring sync frequency. The contributions shown
in Table 1 can be assumed.
Table 1
Calculation of fo total spread
Result for 50 to 110 Hz application:
CONTRIBUTING ELEMENTS
%
Minimum frequency offset between fo and
the lowest trigger frequency
10
Spread of IC
±3
Spread of R (22 k
Ω)
±1
Spread of C (0.1
µF)
±5
Total
19
f
o
50 Hz
1.19
---------------
42 Hz
==
Table 2
VGA modes
MODE
HORIZONTAL/VERTICAL
SYNC POLARITY
HORIZONTAL
FREQUENCY
(kHz)
VERTICAL
FREQUENCY
(Hz)
NUMBER OF
ACTIVE LINES
MODE
OUTPUT PIN 7
1+/
31.45
70
350
LOW
2
−/+
31.45
70
400
LOW
3
−/−
31.45
60
480
LOW
4
+/+
fixed by external circuitry
−−
HIGH




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