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TDA4855 Datasheet(PDF) 6 Page - NXP Semiconductors

Part No. TDA4855
Description  Autosync Deflection Controller ASDC
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Maker  PHILIPS [NXP Semiconductors]

 6 page
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1996 Jul 18
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
Horizontal sync separator and polarity correction
HSYNC (pin 15) is the input for horizontal synchronization
signals, which can be DC-coupled TTL signals (horizontal
or composite sync) and AC-coupled negative-going video
sync signals. Video syncs are clamped to 1.28 V and
sliced at 1.4 V. This results in a fixed absolute slicing level
of 120 mV related to sync top.
For DC-coupled TTL signals the input clamping current is
limited. The slicing level for TTL signals is 1.4 V.
The separated sync signal (either video or TTL) is
integrated on an internal capacitor to detect and normalize
the sync polarity.
Normalized horizontal sync pulses are used as input
signals for the vertical sync integrator, the PLL1 phase
detector and the frequency-locked loop.
Vertical sync integrator
Normalized composite sync signals from HSYNC are
integrated on an internal capacitor in order to extract
vertical sync pulses. The integration time is dependent on
the horizontal oscillator reference current at HREF
(pin 28). The integrator output directly triggers the vertical
oscillator. This signal is available at VSYNC (normally
vertical sync input; pin 14), which is used as an output in
this mode.
Vertical sync slicer and polarity correction
Vertical sync signals (TTL) applied to VSYNC (pin 14) are
sliced at 1.4 V. The output signal of the sync slicer is
integrated on an internal capacitor to detect and normalize
the sync polarity.
If a composite sync signal is detected at HSYNC, VSYNC
is used as output for the integrated vertical sync (e.g. for
power saving applications).
Video clamping/vertical blanking generator
The video clamping/vertical blanking signal at CLBL
(pin 16) is a two-level sandcastle pulse which is especially
suitable for video ICs such as the TDA488X family, but
also for direct applications in video output stages.
The upper level is the video clamping pulse, which is
triggered by the trailing edge of the horizontal sync pulse.
The width of the video clamping pulse is determined by an
internal monoflop.
The lower level of the sandcastle pulse is the vertical
blanking pulse, which is derived directly from the internal
oscillator waveform. It is started by the vertical sync and
stopped with the start of the vertical scan. This results in
optimum vertical blanking.
Blanking will be activated continuously, if one of the
following conditions is true:
No horizontal flyback pulses at HFLB (pin 1)
X-ray protection is activated
Soft start of horizontal drive (voltage at HPLL2 (pin 31)
is low)
Supply voltage at VCC (pin 9) is low (see Fig.14)
PLL1 is unlocked while frequency-locked loop is in
search mode.
Blanking will not be activated if the horizontal sync
frequency is below the valid range or there are no sync
pulses available.
VGA mode detector
The polarities of horizontal and vertical sync are internally
detected in order to provide an automatic adjustment of
vertical size for VGA350 and VGA400 modes.
These automatic VGA presets are activated only if the
current ratio IHBUF/IHREF exceeds a fixed value
(see Chapter “Characteristics”). Thus it is possible to
disable this function for a part of the frequency range or
even completely.
Table 1
VGA modes

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