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TDA4855 Datasheet(PDF) 7 Page - NXP Semiconductors

Part No. TDA4855
Description  Autosync Deflection Controller ASDC
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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 7 page
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1996 Jul 18
7
Philips Semiconductors
Preliminary specification
Autosync Deflection Controller (ASDC)
TDA4855
Frequency-locked loop
The frequency-locked loop can lock the horizontal
oscillator over a wide frequency range. This is achieved by
a combined search and PLL operation. The frequency
range is preset by two external resistors and the
recommended maximum ratio is
Larger ranges are possible by extended applications.
Without a horizontal sync signal the oscillator will be
free-running at fmin. Any change of sync conditions is
detected by the internal coincidence detector. A deviation
of more than 4% between horizontal sync and oscillator
frequency switches the horizontal section into search
mode. This means that PLL1 control currents are switched
off immediately. Then the internal frequency detector
starts tuning the oscillator. Very small DC currents at
HPLL1 (pin 26) are used to perform this tuning with a well
defined change rate. When coincidence between
horizontal sync and oscillator frequency is detected, the
search mode is replaced by a normal PLL operation.
This operation ensures a smooth tuning and avoids fast
changes of horizontal frequency during catching.
In this concept it is not allowed to load HPLL1.
The frequency dependent voltage at this pin is fed
internally to HBUF (pin 27) via a sample-and-hold and
buffer stage. The sample-and-hold stage removes all
disturbances caused by horizontal sync or composite
vertical sync from the buffered voltage. An external
resistor from HBUF to HREF defines the frequency range.
See also hints for locking procedure in note 3 of
Chapter “Characteristics”.
PLL1 phase detector
The phase detector is a standard type using switched
current sources. It compares the middle of horizontal sync
with a fixed point on the oscillator sawtooth voltage.
The PLL1 loop filter is connected to HPLL1 (pin 26).
Horizontal oscillator
The horizontal oscillator is of the relaxation type and
requires a capacitor of 10 nF at HCAP (pin 29).
For optimum jitter performance the value of 10 nF must not
be changed.
The maximum oscillator frequency is determined by a
resistor from HREF to ground. A resistor from HREF to
HBUF defines the frequency range.
f
min
f
max
-----------
1
3.5
--------
=
The reference current at HREF also defines the integration
time constant of the vertical sync integration.
Calculation of line frequency range
First the oscillator frequencies fmin and fmax have to be
calculated. This is achieved by adding the spread of the
relevant components to the highest and lowest sync
frequencies fS(min) and fS(max). The oscillator is driven by
the difference of the currents in RHREF and RHBUF. At the
highest oscillator frequency RHBUF does not contribute to
the spread. The spread will increase towards lower
frequencies due to the contribution of RHBUF. It is also
dependent on the ratio
The following example is a 31.45 to 64 kHz application:
Table 2
Calculation of total spread
Thus the typical frequency range of the oscillator in this
example is:
The resistors RHREF and RHBUF can be calculated with the
following formulae:
Where:
spread of:
for fmax
for fmin
IC
3%
3%
CHCAP
2%
2%
RHREF
1%
RHREF, RHBUF
1%
× (2.3 × nS − 1)
Total
6%
8.69%
n
S
f
S max
()
f
Smin
()
-------------------
=
n
S
f
S max
()
f
Smin
()
-------------------
64 kHz
31.45 kHz
---------------------------
2.04
==
=
f
max
f
Smax
()
1.06
×
67.84 kHz
==
f
min
f
Smin
()
1.087
------------------
28.93 kHz
==
R
HREF
74
kHz
k
×
×Ω
f
max kHz
[]
--------------------------------------
1.091 k
==
R
HBUF
R
HREF
1.19
×
n
×
n1
---------------------------------------------
2.26 k
==
n
f
max
f
min
-----------
2.35
==




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