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TDA4857PS Datasheet(PDF) 9 Page - NXP Semiconductors

Part No. TDA4857PS
Description  I2C-bus autosync deflection controller for PC monitors
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Maker  PHILIPS [NXP Semiconductors]

 9 page
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2000 Jan 31
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
X-ray protection
The X-ray protection input XRAY (pin 2) provides a voltage
detector with a precise threshold. If the input voltage at
XRAY exceeds this threshold level for a certain time then
control bit SOFTST is reset, which switches the IC into
protection mode. In this mode several pins are forced into
defined states:
HUNLOCK (pin 17) is floating
The capacitor connected to HPLL2 (pin 30) is
Horizontal output stage (HDRV) is floating
B+ control driver stage (BDRV) is floating
Vertical output stages (VOUT1 and VOUT2) are floating
CLBL provides a continuous blanking signal.
There are two different methods of restarting the IC:
1. XSEL (pin 9) is open-circuit or connected to ground.
The control bit SOFTST must be set to logic 1 via the
I2C-bus. The IC then returns to normal operation via
soft start.
2. XSEL (pin 9) is connected to VCC via an external
resistor. The supply voltage of the IC must be switched
off for a certain period of time before the IC can be
restarted again using the standard power-on
Vertical oscillator and amplitude control
This stage is designed for fast stabilization of vertical size
after changes in sync frequency conditions.
The free-running frequency ffr(V) is determined by the
resistor RVREF connected to pin 23 and the capacitor
CVCAP connected to pin 24. The value of RVREF is not only
optimized for noise and linearity performance in the whole
vertical and EW section, but also influences several
internal references. Therefore the value of RVREF must not
be changed.
Capacitor CVCAP should be used to select the free-running
frequency of the vertical oscillator in accordance with the
following formula:
To achieve a stabilized amplitude the free-running
frequency ffr(V), without adjustment, should be at least 10%
lower than the minimum trigger frequency.
The contributions shown in Table 2 can be assumed.
Table 2
Calculation of ffr(V) total spread
Result for 50 to 160 Hz application:
The AGC of the vertical oscillator can be disabled by
setting control bit AGCDIS via the I2C-bus. A precise
external current has to be injected into VCAP (pin 24) to
obtain the correct vertical size. This special application
mode can be used when the vertical sync pulses are
serrated (shifted); this condition is found in some display
modes, e.g. when using a 100 Hz upconverter for video
Application hint: VAGC (pin 22) has a high input
impedance during scan. Therefore, the pin must not be
loaded externally otherwise non-linearities in the vertical
output currents may occur due to the changing charge
current during scan.
Adjustment of vertical size, VGA overscan and EHT
The amplitude of the differential output currents at VOUT1
and VOUT2 can be adjusted via register VSIZE. Register
VOVSCN can activate a +17% step in vertical size for the
VGA350 mode.
VSMOD (pin 21) can be used for a DC controlled EHT
compensation of vertical size by correcting the differential
output currents at VOUT1 and VOUT2. The EW
waveforms, vertical focus, pin unbalance and
parallelogram corrections are not affected by VSMOD.
The adjustments for vertical size and vertical position also
affect the waveforms of the horizontal pincushion, vertical
linearity (S-correction), vertical linearity balance, focus
parabola, pin unbalance and parallelogram correction.
The result of this interaction is that no re-adjustment of
these parameters is necessary after an adjustment of
vertical picture size or position.
fr V
Contributing elements
Minimum frequency offset between ffr(V) and
lowest trigger frequency
Spread of IC
Spread of RVREF
Spread of CVCAP
fr V
50 Hz
42 Hz

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