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TDA4857PS Datasheet(PDF) 11 Page - NXP Semiconductors

Part No. TDA4857PS
Description  I2C-bus autosync deflection controller for PC monitors
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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 11 page
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2000 Jan 31
11
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4857PS
Output stage for asymmetric correction waveforms
[ASCOR (pin 20)]
This output is designed as a voltage output for
superimposed waveforms of vertical parabola and
sawtooth. The amplitude and polarity of both signals can
be changed via registers HPARAL and HPINBAL.
Application hint: The TDA4857PS offers two possibilities
to control registers HPINBAL and HPARAL.
1. Control bit ACD = 1
The two registers now control the horizontal phase by
means of internal modulation of the PLL2 horizontal
phase control. The ASCOR output (pin 20) can be left
unused, but it will always provide an output signal
because the ASCOR output stage is not influenced by
the control bit ACD.
2. Control bit ACD = 0
The internal modulation via PLL2 is disconnected.
In order to obtain the required effect on the screen, pin
ASCOR must now be fed to the DC amplifier which
controls the DC shift of the horizontal deflection. This
option is useful for applications which already use a
DC shift transformer.
If the tube does not need HPINBAL and HPARAL, then pin
ASCOR can be used for other purposes, i.e. for a simple
dynamic convergence.
Dynamic focus section [FOCUS (pin 32)]
This section generates a complete drive signal for dynamic
focus applications. The amplitude of the vertical parabola
is independent of frequency and tracks with all vertical
adjustments. The amplitude can be adjusted via register
VFOCUS. FOCUS (pin 32) is designed as a voltage output
for the vertical parabola.
B+ control function block
The B+ control function block of the TDA4857PS consists
of an Operational Transconductance Amplifier (OTA), a
voltage comparator, a flip-flop and a discharge circuit. This
configuration allows easy applications for different B+
control concepts. See also Application Note AN96052:
“B+
converter Topologies for Horizontal Deflection and EHT
with TDA4855/58”.
GENERAL DESCRIPTION
The non-inverting input of the OTA is connected internally
to a high precision reference voltage. The inverting input is
connected to BIN (pin 5). An internal clamping circuit limits
the maximum positive output voltage of the OTA.
The output itself is connected to BOP (pin 3) and to the
inverting input of the voltage comparator.
The non-inverting input of the voltage comparator can be
accessed via BSENS (pin 4).
B+ drive pulses are generated by an internal flip-flop and
fed to BDRV (pin 6) via an open-collector output stage.
This flip-flop is set at the rising edge of the signal at HDRV
(pin 8). The falling edge of the output signal at BDRV has
a defined delay of td(BDRV) to the rising edge of the HDRV
pulse (see Fig.21). When the voltage at BSENS exceeds
the voltage at BOP, the voltage comparator output resets
the flip-flop and, therefore, the open-collector stage at
BDRV is floating again.
An internal discharge circuit allows a well defined
discharge of capacitors at BSENS. BDRV is active at a
LOW-level output voltage (see Figs 21 and 22), thus it
requires an external inverting driver stage.
The B+ function block can be used for B+ deflection
modulators in many different ways. Two popular
application combinations are as follows:
• Boost converter in feedback mode (see Fig.21)
In this application the OTA is used as an error amplifier
with a limited output voltage range. The flip-flop is set on
the rising edge of the signal at HDRV. A reset will be
generated when the voltage at BSENS, taken from the
current sense resistor, exceeds the voltage at BOP.
If no reset is generated within a line period. The rising
edge of the next HDRV pulse forces the flip-flop to reset.
The flip-flop is set immediately after the voltage at
BSENS has dropped below the threshold voltage
VRESTART(BSENS).




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