ABX0235/37/38/39

750kHz – 800MHz Low Phase Noise Multiplier XO

Universal Low Phase Noise IC’s

30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 1

FEATURES

• Selectable 750kHz to 800MHz range.

• Low phase noise output (@ 10kHz frequency

offset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for

106.25MHz, -125dBc/Hz for 155.52MHz, -

110dBc/Hz for 622.08MHz).

• CMOS (ABX0237), PECL (ABX0235 and

ABX0238) or LVDS (ABX0239) output.

• 12 to 25MHz crystal input.

• No external load capacitor required.

• Output Enable selector.

• Selectable 1/16 to 32x frequency multiplier.

• 3.3V operation.

• Available in 16-Pin (TSSOP or 3x3mm QFN).

DESCRIPTION

The ABX0235 (PECL with inverted OE), ABX0237

(CMOS), ABX0238 (PECL), and ABX0239 (LVDS)

are high performance and low phase noise XO IC

chips. They provide phase noise performance as low

as –125dBc at 1kHz offset (at 155MHz) and a typical

RMS jitter of 4pS RMS ( at 155MHz ). They accept

fundamental parallel resonant mode crystals from 12

to 25MHz.

BLOCK DIAGRAM

PIN CONFIGURATION

(Top View)

^: Internal pull-up

*: On 3x3 package, ABX0235/38 do not have SEL0 available: Pin 10

is VDD, pin 11 is GND. However, ABX0237/39 have SEL0 (pin

10), and pin 11 is VDD. See pin assignment table for details.

OUTPUT ENABLE LOGICAL LEVELS

Part #

OE

State

0 (Default)

Output enabled

ABX0238

1

Tri-state

0

Tri-state

ABX0235

ABX0237

ABX0239

1 (Default)

Output enabled

OE input: Logical states defined by PECL levels for ABX0238

Logical states defined by CMOS levels for

ABX0235/37/39

1

2

3

4

5

6

7

8

VDD

9

10

11

12

13

14

15

16

XIN

XOUT

SEL3^

SEL2^

OE

GND

GND

SEL0^

SEL1^

GND

CLKC

VDD

CLKT

GND

GND

ABX023x

GND

VDD

CLKT

CLKC

12

3

4

12

11

10

9

13

14

15

16

8

7

6

5

SEL3^

XOUT

SEL2^

OE

XIN

XOUT

OE

Q

Q

PLL by-pass

SEL

PLL

(Phase

Locked

Loop)

Oscillator

Amplifier