(Preliminary)

ABV8068/69

320-640MHz Low Phase Noise VCXO

30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 9/1/05 Page 8

LAYOUT RECOMMENDATIONS

PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION

The following guidelines are to assist you with a performance optimized PCB design:

-

Keep all the PCB traces to ABV80 as short as

possible, as well as keeping all other traces as

far away from it as possible.

-

Place the crystal as close as possible to both

crystal pins of the device. This will reduce the

cross-talk between the crystal and the other

signals.

-

Separate crystal pin traces from the other signals

on the PCB, but allow ample distance between

the two crystal pin traces.

-

Place a 0.01µF~0.1µF decoupling capacitor

between VDD and GND, on the component side

of the PCB, close to the VDD pin. It is not

recommended to place this component on the

backside of the PCB. Going through vias will

reduce the signal integrity, causing additional

jitter and phase noise.

-

It is highly recommended to keep the VDD and

GND traces as short as possible.

-

Please contact Abracon for the application note

on how to design outputs driving long traces or

the Gerber files for the ABV80 layout.

ABV806X

(VCXO)

16-pin TSSOP

ABV806X

(VCXO)

3x3 QFN