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TDA4886A Datasheet(PDF) 11 Page - NXP Semiconductors

Part No. TDA4886A
Description  140 MHz video controller with I2C-bus
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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 11 page
background image
1998 Dec 04
11
Philips Semiconductors
Product specification
140 MHz video controller with I2C-bus
TDA4886A
10 CHARACTERISTICS
All voltages and currents are measured in a dedicated test circuit which is optimized for best high frequency
performance; all voltages are measured with respect to GND (pins 9 and 14); VP =VP1, 2, 3 = 8 V (pins 7, 21,
18 and 15); Tamb =25 °C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; nominal colour signals at signal
outputs (pins 22, 19 and 16); reference black level (Vrbl) approximately 0.77 V; nominal settings for brightness and
contrast; maximum settings for OSD contrast and gain; no subcontrast, modulation of contrast or limiting (V24 ≥ 5 V);
no OSD fast blanking (pin 1 connected to ground); notes 1 to 3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VP
supply voltage (pin 7)
7.6
8.0
8.8
V
IP
supply current (pin 7)
note 4
21
25
mA
VP1,2,3
channel supply voltage
(pins 21, 18 and 15)
7.6
8.0
8.8
V
IP1,2,3
channel supply current
(pins 21, 18 and 15)
signal outputs (pins 22,
19 and 16) open-circuit;
Vrbl ≈ 0.77 V; notes 4 and 5
21
25
mA
VPSO
supply voltage for signal switch
off (threshold at pin 7)
signal outputs switched to
switch-off voltage
−−
7.2
V
Input clamping and vertical blanking input, validation of buffered I2C-bus data (pin 5)
V5
input clamping and vertical
blanking input signal
notes 6 and 7
no vertical blanking,
no input clamping
−0.1
+1.2
V
vertical blanking,
no input clamping
1.6
2.6
V
input clamping,
no vertical blanking
3.5
VP
V
I5
input current
V5 =1V
−−0.2
−µA
pin 5 connected to ground;
note 8
−80
−60
−30
µA
V5 = −0.1 V; note 8
−250
−200
−100
µA
tr/f5
rise/fall time for input clamping
pulse, disable for vertical
blanking
note 6; see Fig.7
−−
75
ns/V
tW5
width of input clamping pulse
0.6
−−µs
tW5I2C
width of vertical blanking pulse
for validation of buffered
I2C-bus data
leading and trailing edge
threshold V5 = 1.4 V; note 7
10
−−µs
tI2Cvalid
delay between leading edge of
vertical blanking pulse and
validation of buffered I2C-bus
data
I2C-bus transmission in
buffered mode completed;
leading edge threshold
V5 = 1.4 V; note 7
−−
2
µs
tI2Cdead
dead time of I2C-bus receiver
after synchronizing vertical
blanking pulse in case of a
completed I2C-bus transmission
in buffered mode
leading edge threshold
V5 = 1.4 V; note 7
15
−−µs




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