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LX8385-XXIDD Datasheet(PDF) 2 Page - Microsemi Corporation |
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LX8385-XXIDD Datasheet(HTML) 2 Page - Microsemi Corporation |
2 / 11 page PRODUCTION DATA SHEET Microsemi Inc. Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 Copyright © 2000 Rev. 2.0b, 2005-10-25 LX8385x-xx 3A Low Dropout Positive Regulators TM ® ABSOLUTE MAXIMUM RATINGS (NOTE 1) Power Dissipation ................................................................................... Internally Limited Input Voltage ................................................................................................................ 10V Input to Output Voltage Differential............................................................................. 10V Operating Junction Temperature................................................................................150°C Storage Temperature Range....................................................................... -65°C to 150 °C Peak Package Solder Reflow Temp (40 seconds max. exposure) .................260°C (+0, -5) Note 1: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. TH ERMAL DATA DD Plastic TO-263 3-Pin THERMAL RESISTANCE -JUNCTION TO AMBIENT, θ JA 60 °C/W THERMAL RESISTANCE -JUNCTION TO TAB, θ JT 2.7°C/W P Plastic TO-220 3-Pin THERMAL RESISTANCE -JUNCTION TO AMBIENT, θ JA 60 °C/W THERMAL RESISTANCE -JUNCTION TO TAB, θ JT 2.7°C/W DT Plastic TO-252 3-Pin THERMAL RESISTANCE -JUNCTION TO AMBIENT, θ JA 60 °C/W THERMAL RESISTANCE -JUNCTION TO TAB, θ JT 2.7°C/W Junction Temperature Calculation: TJ = TA + (PD x θJT). The θJA & θJT numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. PACKAGE PIN OUT 1 V IN ADJ / GND* V OUT 2 3 TAB is V OUT DD PACKAGE (3-PIN) (Top View) V IN V OUT ADJ/ GND* TAB is V OUT 3 2 1 DT PACKAGE (3-PIN) (Top View) TAB is V OUT ADJ / GND* V OUT V IN 1 2 3 P PACKAGE (3-PIN) (Top View) *Pin 1 is GND for fixed voltage versions RoHS 100% Matte Tin Lead Finish BLOCK DIAGRAM Thermal Limit Circuit Bias Circuit Bandgap Circuit Control Circuit Output Circuit SOA Protection Circuit Current Limit Circuit V IN ADJ or GND* V OUT *Pin 1 is GND for fixed voltage versions |
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