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TDA4887 Datasheet(PDF) 10 Page - NXP Semiconductors

Part No. TDA4887
Description  160 MHz bus-controlled monitor video preamplifier
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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 10 page
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2001 Oct 19
10
Philips Semiconductors
Product speciļ¬cation
160 MHz bus-controlled monitor video
preampliļ¬er
TDA4887PS
7.6
Clamping and blanking pulses
There are two pins for clamping and blanking purposes
(pins CLI and HFB):
1. Pin CLI (input clamping, vertical blanking)
The pin CLI of TDA4887PS can be connected directly
to pin CLBL of e.g. TDA4855 sync processor for input
clamping pulses and vertical blanking pulses.
Input clamping pulses and blanking pulses are
completely separated from the sandcastle input, that
means there is normally (outside detected vertical
blanking) no blanking during input clamping and the
clamping pulse is not suppressed during vertical
blanking.
The input pulse is scanned with two thresholds:
a) 1.4 V (typical) for vertical blanking
b) 3 V (typical) for input clamping.
In order to separate the vertical blanking pulse from
the sandcastle pulse it is necessary that the input
clamping pulse has rise/fall times faster than 75 ns/V
during the transition from 1.2 to 3.5 V and vice versa.
The leading edge of the internal vertical blanking pulse
is delayed by typically 270 ns (after the end of an input
clamping pulse or the beginning of a separate blanking
pulse), the trailing edge is delayed by typically 115 ns.
During the vertical blanking pulse signal blanking,
brightness blanking and pedestal blanking will be
activated. In buffered mode, the leading edge of the
internal vertical blanking pulse is used to synchronize
data transmitted via the I2C-bus (see Section 7.10.1).
For correct input clamping the input signals have to be
at black level during the input clamping pulse.
2. Pin HFB (output clamping and blanking)
The input pulse (e.g. horizontal flyback pulse) is
scanned with two thresholds. If the input pulse
exceeds the first threshold (typically 1.4 V) signal
blanking, brightness blanking and pedestal blanking
will be activated. If the input pulse exceeds the second
threshold (typically 3 V) output clamping will be
activated additionally.
Especially for applications with DC-coupled cathodes
(FPOL = 0), it is useful that the leading edge of the
(internal) clamping pulse is slightly delayed with
respect to the leading edge of the (internal) blanking
pulse in order to avoid initial misclamping due to the
delay of the feedback signal from the cathodes.
7.7
On Screen Display insertion and OSD contrast
On Screen Display (OSD) insertion and OSD contrast are
controlled by a 4-bit DAC driven via the I2C-bus.
If the fast blanking input signal at pin FBL exceeds the
threshold (typically 1.4 V) the input signals are blanked
(signal blanking) and OSD signals are enabled. Then, any
signal at pins OSD1, OSD2 or OSD3 exceeding the same
threshold will create an insertion signal with an amplitude
of 100% of the maximum colour signal. The amplitude can
be controlled by OSD contrast (driven via the I2C-bus) with
a range of 12 dB. The OSD signals are inserted at the
same point as the contrast-controlled input signals and will
be treated with brightness and gain control as with normal
input signals.
Identical pulses at OSD signal input pins and FBL have to
be handled very carefully. Each difference in pulse delay
at the inputs will produce glitches at pulse edges at signal
outputs.
When control bit DISO = 1 the OSD signal insertion and
fast blanking (pin FBL) are disabled.
7.8
Subcontrast adjustment, contrast modulation
and beam current limiting
The pin LIM is a linear contrast control pin which allows
subcontrast setting, contrast modulation and beam current
limiting. The maximum contrast is defined by the actual
I2C-bus setting. Input signals at pin LIM act on video and
OSD signals and do not affect the contrast bit resolution.
If the pin is not used it should be decoupled with a
capacitor or tied to the supply voltage.
7.8.1
BEAM CURRENT LIMITING
The open-circuit voltage is approximately 5 V, contrast
reduction starts at input voltages <4.4 V (typical) and
signal amplification will be reduced with descending input
voltages. The input resistance of pin LIM is very high to
make it possible to choose a time constant sufficient for the
open-circuit voltage to recover through the application.
7.8.2
SUBCONTRAST
In order to fit the maximum signal amplification to the post
amplifier gain, an input voltage of <4.4 V can be used.
7.8.3
CONTRAST MODULATION
To achieve brightness uniformity over the screen, scan
dependent contrast modulation is possible. The nominal
input voltage should be <4.4 V having enough margin for
positive and negative modulation.




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