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TDA5155X Datasheet(PDF) 9 Page - NXP Semiconductors

Part No. TDA5155X
Description  Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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 9 page
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1997 Apr 08
9
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5155
8.3
Sleep mode
In sleep mode, the device is accessible via the serial
interface. All circuits are inactive, except the circuits of the
CMOS serial interface and the circuitry which forces the
data registers to their default values at power-up and
which fixes the DC level of outputs RDx and RDy (required
when operating with more than one amplifier). Typical
static current consumption is
−30 µA. Dynamic current
consumption during operation of the serial interface in
sleep mode due to external activity at the inputs to the
serial interface is not included. In all modes, including the
sleep mode, data registers can be programmed. Sleep is
the default mode at power-up. Switching to other modes
takes less than 0.1 ms.
8.4
Standby mode
The circuit can be put in standby mode using the serial
interface. In standby mode, the typical DC current
consumption is 330
µA. Transients from standby mode to
active mode are two orders of magnitude shorter than from
sleep mode to active mode. This is important in the case
of cylinder mode operation with multiple amplifiers.
All amplifiers can operate from standby mode and all head
switch times can be kept just as short as in the case of
operation with a single amplifier. Head switch times are
summarized in the switching characteristics.
8.5
Active mode
Active mode is either read mode or write mode depending
on the status of the R/W pin.
8.6
Bi-directional serial interface
The serial interface is used for programming the device
and for reading of status information. 16 bits (8 bits for
data and 8 for address) are used to program the device.
The serial interface requires 3 pins: SDATA, SCLK and
SEN. These pins (and R/W as well) are CMOS inputs.
The logic input R/W has an internal 20 k
Ω pull-up resistor
and the SEN logic input has an internal 20 k
Ω pull-down
resistor. Thus, in case the SEN line is opened, no data will
be registered and in case the R/W line is opened, the
device will never be in write mode.
SDATA: serial data; bi-directional data interface. In all
circumstances, the LSB is transmitted first.
SCLK: serial clock; 25 MHz clock frequency.
SEN: serial enable; data transfer takes place when SEN is
HIGH. When SEN is LOW, data and clock signals are
prohibited from entering the circuit.
Three phases in the communication are distinguishable:
addressing, programming and reading. Each
communication sequence starts with an addressing
phase, followed by either a programming phase or a
reading phase.
8.6.1
ADDRESSING
When SEN goes HIGH, bits are latched in at rising edges
of SCLK. The first eight bits a7 to a0 (starting with a0) are
shifted serially into an address register. If SEN goes LOW
before 16 bits have been received, the operation is
ignored. When more than 16 bits (address and data) are
latched in before SEN goes LOW, the first 8 bits are
interpreted as an address and the last 8 bits as data. SEN
should go HIGH at least 5 ns before the first rising edge of
SCLK. Data should be valid at least 5 ns before and after
a rising edge of SCLK. The first six bits a5 to a0 constitute
the register address. Bit a6 is unused. If bit a7 = logic 0,
a PROGRAMMING sequence starts. If bit a7 = logic 1,
READING data from the pre-amplifier can start.
8.6.2
PROGRAMMING DATA
If a7 = 0, the last eight bits d7 to d0 before SEN goes LOW
are shifted into an input register. When SEN goes LOW,
the communication sequence is ended and the data in the
input register is copied in parallel to the data register that
corresponds to the decoded address a0 to a5. SEN
should go LOW at least 5 ns after the last rising edge of
SCLK. See Fig.3 for the timing diagram of the
programming.
8.6.3
READING DATA
Immediately after the IC detects that a7 = logic 1, data
from the data register (address a5 to a0) is copied in
parallel to the input register. Two wait clock cycles must
follow before the controller can start inputting data. At the
first falling edge of SCLK after the 2 wait rising edges of
SCLK, the LSB d0 is placed on SDATA line followed by d1
at the next falling edge of SCLK etc. If SEN goes LOW
before 8 address bits (a7 to a0) have been detected, the
communication is ignored. If SEN goes LOW before the
8 data bits have been sent out of the IC, the reading
sequence is immediately interrupted. See Fig.4 for the
timing diagram of the reading via the serial interface.




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