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TDA5153BG Datasheet(PDF) 10 Page - NXP Semiconductors

Part No. TDA5153BG
Description  Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo 

 10 page
background image
1997 Jul 02
10
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
8
FUNCTIONAL DESCRIPTION
8.1
Read mode
The read mode disables the write circuitry to save power
while reading. The read circuitry is de-activated for write,
sleep and standby modes. The read circuitry may also be
biased during write mode to shorten transients.
The selected head is connected to a multiplexed low-noise
read amplifier. The read amplifier has low-impedance
inputs nRx and nRy (n is the number of the head) and
low-impedance outputs RDx and RDy. The signal polarity
is non-inverting from x and y inputs to x and y outputs.
Ambient magnetic fields at the MR elements result in a
relative change in MR resistance
This change produces a current variation
,
where IMR is the bias current in the MR element.
The current variation is amplified to form the read data
output signal voltage, which is available at RDx
− RDy.
AC coupling between MR elements and amplifier stages
prevents the amplifier input stages from overload by DC
voltages across the MR elements. A fast settling
procedure shortens DC settling transients.
An on-chip generated stable temperature reference
voltage (1.32 V), available at the Rext pin, is dropped
across an external resistor (10 k
Ω) to form a global
reference current for the write and the MR bias currents.
The MR bias current DACs are programmed through the
serial interface according to the following formula
(in mA), where d4 to d0 are bits (either logic 0 or logic 1).
At power-up, all bits are set to logic 0, which results in a
default MR current of 5 mA. The adjustable range of the
MR currents is 5 mA to 20.5 mA. The MR bias currents are
equal for the two stripes of each head. The gain amplifier
is 1-bit programmable. The amplifier gain can be set to its
nominal value or to the nominal value +3 dB.
8.2
Write mode
To minimize power dissipation, the read circuitry may be
disabled in write mode. The write circuitry is disabled in
∆R
MR
R
MR
----------------
∆I
MR
I
MR
=
∆R
MR
R
MR
----------------
×
I
MR
10 k
2R
ext
------------------- 10
16 d4
8d3
4d2
2d1
d0
+
++++
()
=
read, sleep and standby modes. In write mode, a
programmable current is forced through the selected two
terminals inductive write head. The push-pull output
drivers yield near rail-to-rail voltage swing for fast current
polarity switching.
The differential write data input WDIx
− WDIy is PECL
(Positive Emitter Coupled Logic) compatible. The write
data flip-flop can either be used or passed-by. In the case
that the write data flip-flop is used, current polarity is
toggled at the falling edges of the Vdata =VWDIx − VWDIy.
Switching to Write Mode initializes the data flip-flop so that
the write current flows in the write head from x to y. In the
case that the write data flip-flop is not used, the signal
polarity is non-inverting from x and y inputs to x and y
outputs.
The write current magnitude is controlled through on-chip
DACs. The write current is defined as follows:
(in mA) where d4 to d0 are bits (either logic 0 or logic 1).
The adjustable range of the write current is 20 mA to
51 mA. At power-up, the default values
d4 = d3 = d2 = d1 = d0 = logic 0 are initialized,
corresponding to IWR = 20 mA. IWR is the current provided
by the write drivers: the current in the write coil and in the
damping resistor together. The static current in the write
coil is
,
where Rh is the resistance of the coil including leads and
Rd is the damping resistor.
8.3
Sleep mode
In sleep mode, the device is accessible via the serial
interface. All circuits are inactive, except the circuits of the
CMOS serial interface and the circuit which forces the data
registers to their default values at power-up and which
fixes the DC level of RDx
− RDy (required when operating
with more than one amplifier). Typical static current
consumption is
−30 µA. Dynamic current consumption
during operation of the serial interface in the sleep mode
and owing to external activity at the inputs to the serial
interface is not included. In all modes including the sleep
mode, data registers can be programmed. Sleep is the
default mode at power-up. Switching to other modes takes
less than 0.1 ms.
I
WR
10 k
R
ext
---------------- 20
16 d4
8d3
4d2
2d1
d0
+
++++
()
=
I
WR
1
R
h
R
d
-------
+
-----------------




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