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SI2110 Datasheet(PDF) 5 Page - Silicon Laboratories |
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SI2110 Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 94 page Si2107/08/09/10 Preliminary Rev. 0.81 5 Table 3. DC Characteristics (V3.3 = 3.3 V ±10%, V1.8 = 1.8 V ±10%, TA =0–70ºC) Parameter Symbol Test Condition Min Typ Max Unit Supply Current, 3.3 V I3.3 45 Mbaud, CR 7/81 —313 — mA 20 Mbaud, CR 2/31 —298 — mA Supply Current, 1.8 V I1.8 45 Mbaud, CR 7/81 —292 — mA 20 Mbaud, CR 2/31 —217 — mA Input high voltage VIH SCL(25), SDA(26) 2.3 — 5.5 V Input low voltage VIL SCL(25), SDA(26) 0 — 0.8 V Input leakage2 II SCL(25), SDA(26), RESET(11), XTAL1(35), VSEN/ TDET(7) —— ±10 µA Output high voltage VOH 2.4 — — V Output low voltage VOL —— 0.4 V Output leakage IOL —— ±10 µA Notes: 1. LNB dc-dc converter disabled; LNB_EN (CEh[2]) = 0. 2. ISEN(9) is not tested for leakage current. Table 4. RF Electrical Characteristics Parameter Symbol Test Condition Min Typ Max Unit Input power, single channel Pi,ch —–821 –10 dBm Aggregate input power Pi,agg — — –7 dBm Input impedance, balanced Zin ZSOURCE =75 Ω —75 — Ω Return Loss — –10 — dB Dynamic voltage gain range ∆GV —75 — dB Maximum voltage gain GV(max) —55 — dB Noise figure NF Max gain2 — +9.5 +12.5 dB IP3 IP33 Min gain2 +5 +15 — dBm LO leakage LLO 950 to 2150 MHz — — –70 dBm LO SSB phase noise NLO 100 kHz offset — –97 –94 dBc/Hz 1 MHz offset — –97 –94 dBc/Hz LO DSB phase noise (integrated) NLO 10 kHz to 1/2 Baud Rate —2.1 2.8 °rms RF synthesizer spurious At 20 MHz offset — –40 — dBc/Hz LO oscillator settling time ts,LO —100 — µs Notes: 1. For a single channel with SR = 27.5 Mbaud, CR = 7/8, and no added noise. Input power range over which bit error rate is less than 2e-4 after Viterbi decoder. 2. Max gain = 0hFFFF in AGC settings registers (25h–26h). Min gain = 0h0000 in AGC settings registers (25h–26h). 3. IM3 can be calculated as follows: IM3 = 2 x (IP3 – Pin). |
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