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SI5322 Datasheet(PDF) 8 Page - Silicon Laboratories |
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SI5322 Datasheet(HTML) 8 Page - Silicon Laboratories |
8 / 16 page Si5322 8 Preliminary Rev. 0.47 21 CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator. If manual clock selection mode is chosen (AUTOSEL = L), this pin functions as the manual input clock selector. This input is internally deglitched to prevent inadvertent clock switching during changes in the CS input state. 0 = Select CKIN1. 1 = Select CKIN2. If automatic clock selection mode is chosen (AUTOSEL = M or H), this pin indicates which of the two input clocks is cur- rently the active clock. If alarms exist on both CKIN1 and CKIN2, indicating that the digital hold state has been entered, CA will indicate the last active clock that was used before entering the hold state. 0 = CKIN1 active input clock. 1 = CKIN2 active input clock. 23 22 BWSEL1 BWSEL0 I 3-Level Bandwidth Select. Three level inputs that select the DSPLL closed loop band- width. Detailed operations and timing characteristics for these pins may be found in the Any-Rate Precision Clock Family Reference Manual. 27 26 25 24 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 I 3-Level Multiplier Select. Three level inputs that select the input clock and clock multi- plication ratio, depending on the FRQTBL setting. Consult the Any-Rate Precision Clock Family Reference Manual or DSPLLsim configuration software for settings, both avail- able for download at www.silabs.com/timing. 33 30 SFOUT0 SFOUT1 I 3-Level Signal Format Select. Three level inputs that select the output signal format (com- mon mode voltage and differential swing) for both CKOUT1 and CKOUT2. Valid settings include LVPECL, LVDS, and CML. Also includes selections for CMOS mode, tristate mode, and tristate/sleep mode. Table 3. Si5322 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description SFOUT[1:0] Signal Format HH Reserved HM Reserved HL CML MH LVPECL MM Reserved ML LVDS LH CMOS LM Tristate/Sleep LL Reserved |
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