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TDA8004AT Datasheet(PDF) 7 Page - NXP Semiconductors |
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TDA8004AT Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 22 page  2004 May 10 7 Philips Semiconductors Product specification IC card interface TDA8004AT FCE660 VDD tW tW Vth2 + Vhys(th2) Vth2 ALARM (internal signal) Fig.3 Alarm as a function of VDD (tW = 10 ms). Clock circuitry The clock signal (CLK) to the card is either derived from a clock signal input on pin XTAL1 or from a crystal up to 26 MHz connected between pins XTAL1 and XTAL2. The frequency may be chosen at fXTAL, 1⁄2fXTAL, 1⁄4fXTAL or 1 ⁄8fXTAL via pins CLKDIV1 and CLKDIV2. The frequency change is synchronous, which means that during transition, no pulse is shorter than 45% of the smallest period and that the first and last clock pulse around the change has the correct width. In the case of fXTAL, the duty factors are dependent on the signal at XTAL1. In order to reach a 45% to 55% duty factor on pin CLK the input signal on XTAL1 should have a duty factor of 48% to 52% and transition times of less than 5% of the input signal period. If a crystal is used with fXTAL, the duty factor on pin CLK may be 45% to 55% depending on the layout and on the crystal characteristics and frequency. In the other cases, it is guaranteed between 45% and 55% of the period. The crystal oscillator runs as soon as the IC is powered-up. If the crystal oscillator is used, or if the clock pulse on XTAL1 is permanent, then the clock pulse will be applied to the card according to the timing diagram of the activation sequence (see Fig.5). If the signal applied to XTAL1 is controlled by the microcontroller, then the clock pulse will be applied to the card by the microcontroller after completion of the activation sequence. Table 1 Clock circuitry definition CLKDIV1 CLKDIV2 CLK 00 1 ⁄8fXTAL 01 1 ⁄4fXTAL 11 1 ⁄2fXTAL 10 fXTAL |
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