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MH8V644AWZJ-5 Datasheet(PDF) 9 Page - Mitsubishi Electric Semiconductor |
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MH8V644AWZJ-5 Datasheet(HTML) 9 Page - Mitsubishi Electric Semiconductor |
9 / 20 page MITSUBISHI LSIs MH8V644AWZJ -5, -6 Preliminary Spec. MITSUBISHI ELECTRIC 25/Feb./1997 FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM MIT-DS-0120-0.0 ( / 20 ) Specifications subject to change without notice. 9 Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24) Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle. 25: tRAS(min) is specified as two cycles of /CAS input are performed. 26: tCP(max) is specified as a reference point only. If tCP ≥ tCP(max),access time is controlled exclusively by tCAC. Limits Parameter Symbol Min Max (Note25) (Note26) 15 51200 /CAS before /RAS Refresh Cycle (Note 27) Limits Parameter Symbol Unit Min Max Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode. -6 -6 Unit ns ns ns ns ns ns tPC tPRWC tRAS tCP tCPRH tCPWD Fast page mode read/write cycle time /RAS low pulse width for read write cycle /CAS high pulse width /RAS hold time after /CAS precharge Delay time, /CAS precharge to W low Fast page mode read write/read modify write cycle time 35 40 100 10 35 75 (Note23) ns ns ns ns tCSR tCHR tRSR tRHR /CAS setup time before /RAS low /CAS hold time after /RAS low Read setup time before /RAS low Read hold time after /RAS low 10 10 10 10 Min Max 10 51200 -5 30 35 85 5 30 70 Min Max -5 5 10 10 10 Read-Write and Read-Modify-Write Cycles Limits Parameter Symbol Unit Min Max -6 (Note22) (Note23) Read write/read modify write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low Delay time, /RAS low to /W low /CAS hole time after /W low tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL ns ns ns ns ns ns ns ns ns ns (Note23) (Note23) 10000 10000 50 150 50 95 0 30 75 45 15 95 Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 23:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS ≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD ≥tCPWD(min) (for Fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is satisfied,the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate. Delay time, address to /W low Min Max -5 10000 10000 50 130 50 85 0 30 65 40 15 85 /RAS hold time after /W low Write pulse width Data setup time before /W loe /OE hold time after /W low tRWL tWP tDS tDH tOEH ns ns ns ns ns 15 10 0 10 15 Data hold time after /W low 15 10 0 10 10 |
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