K4S640832K

Synchronous DRAM

Rev. 1.1 February 2006

3 of 14

K4S641632K

Part No.

Orgainization

Max Freq.

Interface

Package

K4S640832K-T(U)C/L75

8Mb x 8

133MHz(CL=3)

LVTTL

54pin TSOP(II)

Pb (Pb-free)

K4S641632K-T(U)C/L50

4Mb x 16

200MHz(CL=3)

K4S641632K-T(U)C/L60

166MHz(CL=3)

K4S641632K-T(U)C/L75

133MHz(CL=3)

The K4S640832K / K4S641632K is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8

bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG

′s high performance CMOS technology. Synchronous design allows

precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies,

programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock

• Burst read single-bit write operation

• DQM (x8) & L(U)DQM (x16) for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

• Pb/Pb-free Package

• RoHS compliant for Pb-free Package

GENERAL DESCRIPTION

FEATURES

Ordering Information

2M x 8Bit x 4Banks / 1M x 16Bit x 4Banks SDRAM

Row & Column address configuration

Organization

Row Address

Column Address

8Mx8

A0~A11

A0-A8

4Mx16

A0~A11

A0-A7