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24C32 Datasheet(PDF) 8 Page - Microchip Technology |
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24C32 Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 14 page  24C32 DS21061H-page 8 2004 Microchip Technology Inc. 6.3 Contiguous Addressing Across Multiple Devices The device select bits A2, A1, A0 can be used to expand the contiguous address space for up to 256K bits by adding up to eight 24C32's on the same bus. In this case, software can use A0 of the control byte as address bit A12, A1 as address bit A13, and A2 as address bit A14. 6.4 Sequential Read Sequential reads are initiated in the same way as a ran- dom read except that after the 24C32 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. This acknowledge directs the 24C32 to transmit the next sequentially addressed 8 bit word. (Figure 6-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will gen- erate a stop condition. To provide sequential reads the 24C32 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The address pointer, however, will not roll over from address 07FF to address 0000. It will roll from 07FF to unused memory space. 6.5 Noise Protection The SCL and SDA inputs have filter circuits which sup- press noise spikes to ensure proper device operation even on a noisy bus. All I/O lines incorporate Schmitt triggers for 400 kHz (Fast Mode) compatibility. FIGURE 6-2: RANDOM READ FIGURE 6-3: SEQUENTIAL READ SDA LINE BUS CONTROL BYTE WORD ADDRESS (1) S T O P S T A R T A C K A C K A C K ACTIVITY: A C K N O DATA n 00 0 WORD ADDRESS (0) S T A R T CONTROL BYTE A C K 0 S P S P BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY S T O P CONTROL BYTE A C K N O A C K DATA n DATA n + 1 DATA n + 2 DATA n + X A C K A C K A C K |
Similar Part No. - 24C32 |
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Similar Description - 24C32 |
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