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24AA128 Datasheet(PDF) 6 Page - Microchip Technology |
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24AA128 Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 26 page  24AA128/24LC128/24FC128 DS21191P-page 6 © 2007 Microchip Technology Inc. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus Not Busy (A) Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line, while the clock (SCL) is high, determines a Stop condition. All operations must end with a Stop condition. 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device. 4.5 Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this Acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX128) will leave the data line high to enable the master to generate the Stop condition. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS FIGURE 4-2: ACKNOWLEDGE TIMING Note: The 24XX128 does not generate any Acknowledge bits if an internal programming cycle is in progress. Address or Acknowledge Valid Data Allowed to Change Stop Condition Start Condition SCL SDA (A) (B) (D) (D) (C) (A) SCL 9 8 7 6 5 4 3 2 11 2 3 Transmitter must release the SDA line at this point, allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. Receiver must release the SDA line at this point so the Transmitter can continue sending data. Data from transmitter SDA Acknowledge Bit Data from transmitter |
Similar Part No. - 24AA128_07 |
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Similar Description - 24AA128_07 |
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