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TDA8357J Datasheet(PDF) 5 Page - NXP Semiconductors |
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TDA8357J Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 16 page 1999 Nov 10 5 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Notes 1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage. 2. At Tj(max). 3. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor. 4. Equivalent to 100 pF capacitance discharge through a 1.5 k Ω resistor. 5. Internally limited by thermal protection at Tj ≈ 170 °C. THERMAL CHARACTERISTICS In accordance with IEC 747-1. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP supply voltage − 18 V VFB flyback supply voltage − 68 V Vn DC voltage pin OUTA note 1 − 68 V pin OUTB − VP V pins INA, INB, GUARD and FEEDB −0.5 VP V In DC current pins OUTA and OUTB during scan (p-p) − 2.0 A pins OUTA and OUTB at flyback (peak); t ≤ 1.5 ms −±1.2 A pins INA, INB, GUARD and FEEDB −20 +20 mA Ilu latch-up current current into any pin; pin voltage is 1.5 × VP; note 2 − +200 mA current out of any pin; pin voltage is −1.5 × V P; note 2 −200 − mA Ves electrostatic handling voltage machine model; note 3 −300 +300 V human body model; note 4 −2000 +2000 V Ptot total power dissipation − 8W Tstg storage temperature −55 +150 °C Tamb ambient temperature −25 +75 °C Tj junction temperature note 5 − 150 °C SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Rth(j-c) thermal resistance from junction to case −− 6 K/W Rth(j-a) thermal resistance from junction to ambient in free air −− 65 K/W |
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