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MCP3204 Datasheet(PDF) 3 Page - Microchip Technology |
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MCP3204 Datasheet(HTML) 3 Page - Microchip Technology |
3 / 34 page © 2007 Microchip Technology Inc. DS21298D-page 3 MCP3204/3208 Analog Inputs Input Voltage Range for CH0- CH7 in Single-Ended Mode VSS —VREF V Input Voltage Range for IN+ in pseudo-differential Mode IN- — VREF+IN- Input Voltage Range for IN- in pseudo-differential Mode VSS-100 — VSS+100 mV Leakage Current — 0.001 ±1 µA Switch Resistance — 1000 — Ω See Figure 4-1 Sample Capacitor — 20 — pF See Figure 4-1 Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage VIH 0.7 VDD —— V Low Level Input Voltage VIL —— 0.3 VDD V High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5V Low Level Output Voltage VOL —— 0.4 V IOL = 1 mA, VDD = 4.5V Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD Pin Capacitance (All Inputs/Outputs) CIN,COUT —— 10 pF VDD = 5.0V (Note 1) TAMB = 25°C, f = 1 MHz Timing Parameters Clock Frequency fCLK — — — — 2.0 1.0 MHz MHz VDD = 5V (Note 3) VDD = 2.7V (Note 3) Clock High Time tHI 250 — — ns Clock Low Time tLO 250 — — ns CS Fall To First Rising CLK Edge tSUCS 100 — — ns Data Input Setup Time tSU —— 50 ns Data Input Hold Time tHD —— 50 ns CLK Fall To Output Data Valid tDO — — 200 ns See Figures 1-2 and 1-3 CLK Fall To Output Enable tEN — — 200 ns See Figures 1-2 and 1-3 CS Rise To Output Disable tDIS — — 100 ns See Figures 1-2 and 1-3 CS Disable Time tCSH 500 — — ns D OUT Rise Time tR — — 100 ns See Figures 1-2 and 1-3 (Note 1) D OUT Fall Time tF — — 100 ns See Figures 1-2 and 1-3 (Note 1) Power Requirements Operating Voltage VDD 2.7 — 5.5 V Operating Current IDD — — 320 225 400 — µA VDD=VREF = 5V, DOUT unloaded VDD=VREF = 2.7V, DOUT unloaded Standby Current IDDS —0.5 2.0 µA CS = VDD = 5.0V ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE Parameters Sym Min Typ Max Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”, for more information. |
Similar Part No. - MCP3204_07 |
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Similar Description - MCP3204_07 |
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