STM32F101XB datasheet(9/64 Pages) STMICROELECTRONICS

Part #	STM32F101XB

Description	Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces

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STM32F101xx

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External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detectors lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect external line with pulse

width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16

external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is

monitored for failure. During such a scenario, it is disabled and software interrupt

management follows. Similarly, full interrupt management of the PLL clock entry is available

when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the High Speed APB

(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 36 MHz.

Boot modes

At startup, boot pins are used to select one of five boot options:

●

Boot from User Flash

●

Boot from System Memory

●

Boot from SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using the USART.

Power supply schemes

●

VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.

Provided externally through VDD pins.

●

VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs

and PLL. In VDD range (ADC is limited at 2.4 V).

●

VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when VDD is not present.

Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an

external reset circuit.

The device features an embedded Programmable voltage detector (PVD) that monitors the

VDD power supply and compares it to the VPVD threshold. An interrupt can be generated

when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The

interrupt service routine can then generate a warning message and/or put the MCU into a

safe state. The PVD is enabled by software.

Refer to Table 9: Embedded reset and power control block characteristics for the values of

VPOR/PDR and VPVD.

Similar Part No. - STM32F101XB

Manufacturer	Part #	Datasheet	Description
STMicroelectronics	STM32F101XB	1Mb / 74P	Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces
	STM32F101xB	999Kb / 81P	Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces
	STM32F101XB	1Mb / 85P	Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces
	STM32F101xB	1Mb / 89P	Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces

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Similar Description - STM32F101XB

Manufacturer	Part #	Datasheet	Description
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