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AZ100LVEL16VTNB Datasheet(PDF) 9 Page - Arizona Microtek, Inc |
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AZ100LVEL16VTNB Datasheet(HTML) 9 Page - Arizona Microtek, Inc |
9 / 13 page AZ100LVEL16VT April 2007 * REV - 9 www.azmicrotek.com 9 Bottom Center Pad may be left open or tied to VEE. Pin 4 is the VEE return. EN operation follows CMOS/TTL functionality. See Timing Diagram above. D 4mA 470 Ω V BB V EE Q HG Q Q HG MLP 8, 2x2mm AZ100LVEL16VTNC CMOS / TTL THRESHOLD EN D 4 3 2 1 6 5 8 7 MLP 8, 2x2mm AZ100LVEL16VTNC QHG QHG EN Q VBB VEE VCC TOP VIEW Bottom Center Pad is the VEE return. D 4 3 2 1 6 5 8 7 MLP 8, 2x2mm AZ100LVEL16VTND QHG QHG EN Q VBB VCC TOP VIEW D VEE D 4mA 470 VBB VEE QHG Q D QHG MLP 8, 2x2mm AZ100LVEL16VTND 470 CMOS / TTL THRESHOLD EN EN operation follows CMOS/TTL functionality. See Timing Diagram above. LOGIC DIAGRAMS AND PINOUTS FOR 2x2mm PACKAGE |
Similar Part No. - AZ100LVEL16VTNB |
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Similar Description - AZ100LVEL16VTNB |
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