AZ10LVEL33

AZ100LVEL33

ECL/PECL

÷4 Divider

1630 S. STAPLEY DR., SUITE 127

• MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

ARIZONA MICROTEK, INC.

FEATURES

•

Green / RoHS Compliant /

Lead (Pb) Free package available

•

Operating Range of 3.0V to 5.5V

•

470ps Propagation Delay

•

4.0GHz Toggle Frequency

•

Internal Input Pulldown Resistors

•

Direct Replacement for ON Semiconductor

MC10EL33, MC100EL33,

and MC100LVEL33

•

Transistor Count = 91 Devices

•

IBIS Model Files Available on Arizona

Microtek Web Site

DESCRIPTION

The AZ10/100LVEL33 is an integrated

÷4 divider. The RESET pin is asynchronous and clears the output (Q

Low, Q

¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET

allows for the synchronization of multiple LVEL33’s in a system.

¯¯¯¯ differential

input pair. The input signal is then fed to the other CLK/ CLK

NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

LOGIC DIAGRAM

R

÷4

RESET

CLK

Q

CLK

Q

PACKAGE AVAILABILITY

PACKAGE

PART NUMBER

MARKING

NOTES

MLP 8 (2x2) Green

/ RoHS Compliant /

Lead (Pb) Free

AZ100LVEL33NG

C3G

<Date Code>

1,2

MLP 16 (3x3)

AZ10/100LVEL33L

AZM

L33

<Date Code>

1,2

SOIC 8

AZ10LVEL33D

AZM10

LVEL33

1,2,3

SOIC 8

AZ100LVEL33D

AZM100

LVEL33

1,2,3

TSSOP 8

AZ10LVEL33T

AZT

LV33

1,2,3

TSSOP 8

AZ100LVEL33T

AZH

LV33

1,2,3

1

Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K

parts) Tape & Reel.

2

Date code format: “Y” or “YY” for year followed by “WW” for week.

3

Date code “YWW” or “YYWW” on underside of part.

PIN DESCRIPTION

PIN

FUNCTION

CLK, CLK

¯¯¯

Clock Inputs

RESET

Asynchronous Reset

Reference Voltage Output

Q, Q

¯

Data Outputs

Positive Supply

Negative Supply