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AZ100LVEL16VTXP Datasheet(PDF) 2 Page - Arizona Microtek, Inc |
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AZ100LVEL16VTXP Datasheet(HTML) 2 Page - Arizona Microtek, Inc |
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2 / 13 page  AZ100LVEL16VT April 2007 * REV - 9 www.azmicrotek.com 2 Outputs QHG and Q ¯ HG each have an optional on-chip pull-down current source of 10 mA. When pad/pin VEEP is left open (NC), the output current sources are disabled and the QHG /Q ¯ HG operate as standard PECL/ECL. When VEEP is connected to VEE, the current sources are activated. The QHG /Q ¯ HG pull-down current can be decreased, by using a resistor to connect VEEP to VEE. (See graph on page 5.) MLP 8, 2x2 mm Package, VTNA, VTNB, VTNC & VTND Versions All MLP 8, 2x2mm versions of the AZ100LVEL16VT provide an enable input that allows continuous oscillator operation. VTNA and VTNB utilize an enable (EN ¯¯ ) that operates in the PECL/ECL mode. When the EN ¯¯ input is LOW, the Q ¯ and QHG/Q ¯ HG outputs follow the data inputs. When EN ¯¯ is HIGH, the QHG output is forced high and the Q ¯ HG output is forced low. VTNC and VTND utilize an enable (EN) that operates in the CMOS/TTL mode. When the EN input is HIGH, the Q ¯ and QHG/Q ¯ HG outputs follow the data inputs. When EN is LOW, the QHG output is forced high and the Q ¯ HG output is forced low. For VTNA and VTND, both D and D ¯ inputs are brought out and tied to the VBB pin through 470 Ω internal bias resistors. In VTNB and VTNC, the D ¯ input is internally tied directly to the VBB pin and the D input is tied to the VBB pin through a 470 Ω internal bias resistor. Bypassing VBB to ground with a 0.01 μF capacitor is recommended. All MLP 8, 2x2mm versions (VTNA, VTNB, VTNC & VTND) have the Q, QHG, and Q ¯ HG current sources disabled, while the Q ¯ output operates with a 4 mA current source to VEE. NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established. ENABLE TRUTH TABLE MLP 16 (VTL) or DIE (VTX) EN-SEL EN Q/Q ¯ QHG Q ¯ HG NC NC PECL Low, VEE or NC PECL High or VCC Data Data Data High Data Low VEE* VEE* VEE* VEE* CMOS Low or VEE CMOS High or VCC NC, no external pull-up NC, with ≤20kΩ to VCC Data Data Data Data High Data High Data Low Data Low Data *Connections to VCC or VEE must be less than 1Ω. CURRENT SOURCE TRUTH TABLE MLP 16 (VTL) or DIE (VTX) CS-SEL Q Q ¯ NC VEE* VCC* 4mA typ. 8mA typ. 0 4mA typ. 8mA typ. 4mA typ. *Connections to VCC or VEE must be less than 1Ω. PIN DESCRIPTION PIN FUNCTION D/D ¯ Data Inputs Q/Q ¯ Data Outputs QHG/Q ¯ HG Data Outputs w/High Gain VBB Reference Voltage Output EN-SEL Selects Enable Logic EN/EN ¯¯ Enable Input CS-SEL Selects Q and Q ¯ Current Source Magnitude VEEP Optional QHG and Q ¯ HG Current Sources VEE Negative Supply VCC Positive Supply Q D 4mA EA. 470 Ω V BB EN V EE EN-SEL V EEP CMOS / TTL THRESHOLD 10mA EA. CS-SEL Q HG Q D Q HG MLP 16 (VTL) or DIE (VTX) 470 Ω |
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Similar Description - AZ100LVEL16VTXP |
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