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HMXADC9225NZG Datasheet(PDF) 7 Page - Honeywell Solid State Electronics Center |
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HMXADC9225NZG Datasheet(HTML) 7 Page - Honeywell Solid State Electronics Center |
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7 / 11 page  HMXADC9225 7 www.honeywell.com/microelectronics DIGITAL SPECIFICATIONS (AVDD = +5V, DRVDD = +5V, unless otherwise noted) Parameter Symbol Min Typ Max Units LOGIC INPUTS (CLK, OE) High Level Input Voltage (DRVDD = +5V) VIH_50 3.5 V High Level Input Voltage (DRVDD =+3.3V) VIH_33 2.3 V Low Level Input Voltage (DRVDD = +5V) VIL_50 1.0 V Low Level Input Voltage (DRVDD = +3.3V) VIL_33 1.0 V High Level Input Current (DRVDD=5V, VIN=5V) IIH_50 -10 10 µA Low Level Input Current (DRVDD=5V, VIN=0V) IIL_50 -10 10 µA High Level Input Current (DRVDD=3.3V, VIN=3.3V) IIH_33 -10 10 µA Low Level Input Current (DRVDD=3.3V, VIN=0V) IIL_33 -10 10 µA Input Capacitance (1) CIN 5 pF LOGIC OUTPUTS (D1-D12 with DRVDD = +5V) High Level Output Voltage(IOH = 50µA) VOH1_50 4.5 V High Level Output Voltage(IOH = 0.5mA) VOH2_50 2.4 V Low Level Output Voltage(IOL = 1.6mA) VOL2_50 0.4 V Low Level Output Voltage(IOL = 50µA) VOL1_50 0.1 V High Z Output Current (DRVDD=5V, OE=0V, VOUT=5V) IOZH_50 -10 10 µA High Z Output Current (DRVDD=5V, OE=0v, VOUT=0V) IOZL_50 -10 10 µA LOGIC OUTPUTS (D1-D12 with DRVDD = +3.3V) High Level Output Voltage(IOH = 50µA) VOH1_33 2.95 V High Level Output Voltage(IOH = 0.5mA) VOH2_33 2.80 V Low Level Output Voltage(IOL = 1.6mA) VOL2_33 0.4 V Low Level Output Voltage(IOL = 50µA) VOL1_33 0.05 V High Z Output Current (DRVDD=3.3V, VOE=0V, VOUT=3.3V) IOZH_33 -10 10 µA High Z Output Current (DRVDD=3.3V, VOE=0V, VOUT=0V) IOZL_33 -10 10 µA Output Capacitance (1) COUT 5 pF (1) Guaranteed but not tested. DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicate that all 4096 codes, respectively, must be present over all operating ranges. ZERO ERROR The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point. GAIN ERROR The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. TEMPERATURE DRIFT The temperature drift for zero error and gain error specifies the maximum change from the initial (+25°C) value to the value at TMIN or TMAX. APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. APERTURE DELAY Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. |
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