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SMJ320F2812 Datasheet(PDF) 9 Page - Texas Instruments |
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SMJ320F2812 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 138 page  Introduction 9 December 2004 − Revised September 2006 SGUS053B Table 2−2. Signal Descriptions† (Continued) NAME DESCRIPTION PU/PD§ I/O/Z‡ PIN NO. NAME DESCRIPTION PU/PD§ I/O/Z‡ 172-PIN HFG TESTSEL 131 I PD Test Pin. Reserved for TI. Must be connected to ground. XRS 156 I/O PU Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC points to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 XCLKIN cycles. The output buffer of this pin is an open-drain with an internal pullup (100 µA, typical). It is recommended that this pin be driven by an open-drain device. TEST1 66 I/O − Test Pin. Reserved for TI. On F281x devices, TEST1 must be left unconnected. TEST2 65 I/O − Test Pin. Reserved for TI. On F281x devices, TEST2 must be left unconnected. TRST 132 I PD JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device. In a low-noise environment, TRST can be left floating. In a high-noise environment, an additional pulldown resistor may be needed. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-k Ω resistor generally offers adequate protection. Since this is application specific, it is recommended that each target board is validated for proper operation of the debugger and the application. TCK 133 I PU JTAG test clock with internal pullup TMS 123 I PU JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. TDI 128 I PU JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO 124 O/Z − JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK. EMU0 133 I/O/Z PU Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. EMU1 143 I/O/Z PU Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. † Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown |
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