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TSC2004 Datasheet(PDF) 6 Page - Burr-Brown (TI) |
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TSC2004 Datasheet(HTML) 6 Page - Burr-Brown (TI) |
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6 / 54 page  www.ti.com TIMING INFORMATION t HD, STA t SU, DAT t HD, DAT t SU, STA t SU, STO t HD, STA t LOW t HIGH t R t F t BUF SDA START CONDITION START CONDITION STOP CONDITION REPEATED START CONDITION SCL TIMING REQUIREMENTS: I 2C Standard Mode (f SCL = 100kHz) (1) TSC2004 SBAS408A – JUNE 2007 – REVISED AUGUST 2007 Figure 1. Detailed I/O Timing All specifications typical at –40 °C to +85°C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted. 2-WIRE STANDARD MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT SNSVDD ≥ 1.6V 10 μs Reset low time(2) tWL(RESET) 1.2V ≤ SNSVDD < 1.6V 13 μs SCL clock frequency fSCL 100 kHz Bus free time between a STOP and START tBUF 4.7 μs condition Hold time (repeated) START condition tHD, STA 4.0 μs Low period of SCL clock tLOW 4.7 μs High period of the SCL clock tHIGH 4.0 μs Setup time for a repeated START condition tSU, STA 4.7 μs Data hold time tHD, DAT 0 3.45 μs Data setup time tSU, DAT 250 ns Rise time for both SDA and SCL clock signals tR Cb = total bus capacitance 1000 ns (receiving) Fall time for both SDA and SCL clock signals tF Cb = total bus capacitance 300 ns (receiving) Fall time for both SDA and SCL clock signals tOF Cb = total bus capacitance 250 ns (transmitting) Setup time for STOP condition tSU, STO 4.0 μs Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 400 pF Pulse width of spike suppressed tSP N/A N/A ns (1) All input signals are specified with tR = tF = 5ns (10% to 90% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2. (2) Refer to Figure 36. 6 Submit Documentation Feedback |
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