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STK10C48-P35I Datasheet(PDF) 8 Page - Simtek Corporation |
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STK10C48-P35I Datasheet(HTML) 8 Page - Simtek Corporation |
8 / 12 page STK10C48 March 2006 8 Document Control # ML0002 rev 0.2 The STK10C48 has two modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. When in SRAM mode, the mem- ory operates as a standard fast static RAM. While in nonvolatile mode, data is transferred in parallel from SRAM to Nonvolatile Elements or from Nonvolatile Elements to SRAM. NOISE CONSIDERATIONS Note that the STK10C48 is a high-speed memory and so must have a high-frequency bypass capaci- tor of approximately 0.1 μF connected between V CC and V SS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM READ The STK10C48 performs a READ cycle whenever E and G are low and NE and W are high. The address specified on pins A 0-10 determines which of the 2,048 data bytes will be accessed. When the READ is initi- ated by an address transition, the outputs will be valid after a delay of t AVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at t ELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the t AVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high or W or NE is brought low. SRAM WRITE A WRITE cycle is performed whenever E and W are low and NE is high. The address inputs must be sta- ble prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on pins DQ 0-7 will be writ- ten into the memory if it is valid t DVWH before the end of a W controlled WRITE or t DVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers t WLQZ after W goes low. NONVOLATILE STORE A STORE cycle is performed when NE, E and W and low and G is high. While any sequence that achieves this state will initiate a STORE, only W initi- ation (STORE cycle #1) and E initiation (STORE cycle #2) are practical without risking an unintentional SRAM WRITE that would disturb SRAM data. During a STORE cycle, previous nonvolatile data is erased and the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initi- ated, further input and output are disabled and the DQ 0-7 pins are tri-stated until the cycle is complete. If E and G are low and W and NE are high at the end of the cycle, a READ will be performed and the out- puts will go active, signaling the end of the STORE. NONVOLATILE RECALL A RECALL cycle is performed when E, G and NE are low and W is high. Like the STORE cycle, RECALL is initiated when the last of the four clock signals goes to the RECALL state. Once initiated, the RECALL cycle will take t NLQX to complete, during which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. As with the STORE cycle, a transition must occur on any one control pin to cause a RECALL, preventing inadvertent multi-triggering. On power up, once V CC exceeds 4.25V, a RECALL cycle is automatically initi- ated. Due to this automatic RECALL, SRAM operation cannot commence until t RESTORE after VCC exceeds 4.25V. POWER-UP RECALL During power up, or after any low-power condition (V CC < 3.0V), an internal RECALL request will be latched. When V CC once again exceeds 4.25V, a RECALL cycle will automatically be initiated and will take t RESTORE to complete. DEVICE OPERATION |
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