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STK15C68-PF45I Datasheet(PDF) 1 Page - Simtek Corporation |
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STK15C68-PF45I Datasheet(HTML) 1 Page - Simtek Corporation |
1 / 10 page March 2006 1 Document Control # ML0009 rev 0.2 STK15C68 8K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM Obsolete - Not Recommend for new Deisgns FEATURES • Nonvolatile Storage without Battery Problems • Directly Replaces 8K x 8 Static RAM, Battery- Backed RAM or EEPROM • 25ns, 35ns and 45ns Access Times • STORE to Nonvolatile Elements Initiated by Software or AutoStore™ on Power Down • RECALL to SRAM Initiated by Software or Power Restore • 10mA Typical I CC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to Nonvolatile Ele- ments • 100-Year Data Retention over Full Industrial Temperature Range • No Data Loss from Undershoot • Commercial and Industrial Temperatures • 28-Pin 600 or 300 mil PDIP and 350 mil SOIC Packages DESCRIPTION The STK15C68 is a fast SRAM with a nonvolatile ele- ment incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation) can take place automatically on power down using charge stored in system capacitance. Transfers from the Non- volatile Elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initia- tion of STORE and RECALL cycles can also be con- trolled by entering control sequences on the SRAM inputs. The STK15C68 is pin-compatible with 8k x 8 SRAM s and battery-backed SRAMs, allowing direct substitution while enhancing performance. A similar device (STK16C68) with an internally integrated capacitor is available for systems with very fast slew rates. The STK12C68, which uses an external capaci- tor, is an alternative for these applications. BLOCK DIAGRAM COLUMN I/O COLUMN DEC STATIC RAM ARRAY 128 x 512 QUANTUM TRAP 128 x 512 STORE/ RECALL CONTROL STORE RECALL POWER CONTROL A5 A6 A9 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 SOFTWARE DETECT VCC A0 - A12 G E W A8 A7 A10 A3 A2 A0 A1 A4 PIN NAMES A0 - A12 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable VCC Power (+ 5V) VSS Ground PIN CONFIGURATIONS NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VCC NC A8 A9 A11 G W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28 - 300 PDIP 28 - 600 PDIP 28 - 350 SOIC |
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