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DS28E01P-100 Datasheet(PDF) 6 Page - Dallas Semiconductor |
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DS28E01P-100 Datasheet(HTML) 6 Page - Dallas Semiconductor |
6 / 16 page Abridged Data Sheet DS28E01-100 6 of 16 64-BIT LASERED ROM Each DS28E01-100 has a unique ROM Registration Number that is 64 bits long, as shown in Figure 3. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC (Cyclic Redundancy Check) of the first 56 bits. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X 8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire CRC is available in Application Note 27. The shift register bits are initialized to zero. Then starting with the LSB of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros. Figure 3. 64-Bit LASERED ROM MSB LSB 8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code * MSB LSB MSB LSB MSB LSB Figure 4. 1-Wire CRC Generator X 0 X 1 X 2 X 3 X 4 X 5 X 6 X 7 X 8 Polynomial = X 8 + X5 + X4 + 1 1 st STAGE 2 nd STAGE 3 rd STAGE 4 th STAGE 6 th STAGE 5 th STAGE 7 th STAGE 8 th STAGE INPUT DATA MEMORY The DS28E01-100 has four memory areas: data memory, secrets memory, register page with special function registers and user-bytes, and a volatile scratchpad. The data memory is organized as four pages of 32 bytes. Secret and scratchpad are 8 bytes each. The scratchpad acts as a buffer when writing to the data memory, loading the initial secret or when writing to the register page. For further details (including Figures 5 and 6) refer to the full version of the data sheet. * For the actual Family Code refer to the full version of the data sheet. |
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