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CDCE949PWRG4 Datasheet(PDF) 6 Page - Texas Instruments |
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CDCE949PWRG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 31 page www.ti.com DEVICE CHARACTERISTICS (Continued) CDCE949 CDCEL949 SCAS844 – JUNE 2007 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT CDCE949 – LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE VDDOUT = 3 V, IOH = –0.1 mA 2.9 VOH LVCMOS high-level output voltage VDDOUT = 3 V, IOH = –8 mA 2.4 V VDDOUT = 3 V, IOH = –12 mA 2.2 VDDOUT = 3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VDDOUT = 3 V, IOL = 8 mA 0.5 V VDDOUT = 3 V, IOL = 12 mA 0.8 tPLH, Propagation delay PLL bypass 3.2 ns tPHL tr/tf Rise and fall time VDDOUT = 3.3 V (20%–80%) 0.6 ns 1 PLL switching, Y2-to-Y3 60 90 tjit(cc) Cycle-to-cycle jitter(2)(3) ps 4 PLLs switching, Y2-to-Y9 120 170 1 PLL switching, Y2-to-Y3 70 100 tjit(per) Peak-to-peak period jitter (2)(3) ps 4 PLLs switching, Y2-to-Y9 130 180 fOUT = 50 MHz; Y1-to-Y3 60 tsk(o) Output skew(4) ps fOUT = 50 MHz; Y2-to-Y5 or Y6-to-Y9 160 odc Output duty cycle(5) fVCO = 100 MHz; Pdiv = 1 45 55 % CDCE949 – LVCMOS PARAMETER FOR VDDOUT = 2.5 V – MODE VDDOUT = 2.3 V, IOH = –0.1 mA 2.2 VOH LVCMOS high-level output voltage VDDOUT = 2.3 V, IOH = –6 mA 1.7 V VDDOUT = 2.3 V, IOH = –10 mA 1.6 VDDOUT = 2.3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VDDOUT = 2.3 V, IOL = 6 mA 0.5 V VDDOUT = 2.3 V, IOL = 10 mA 0.7 tPLH, Propagation delay PLL bypass 3.4 ns tPHL tr/tf Rise and fall time VDDOUT = 2.5 V (20%–80%) 0.8 ns 1 PLL switching, Y2-to-Y3 60 90 ps tjit(cc) Cycle-to-cycle jitter (2)(3) 4 PLLs switching, Y2-to-Y9 120 170 1 PLL switching, Y2-to-Y3 70 100 ps tjit(per) Peak-to-peak period jitter (2)(3) 4 PLLs switching, Y2-to-Y9 130 180 fOUT = 50 MHz; Y1-to-Y3 60 tsk(o) Output skew(4) ps fOUT = 50 MHz; Y2-to-Y5 or Y6-to-Y9 160 odc Output duty cycle(5) fVCO = 100 MHz; Pdiv = 1 45 55 % (1) All typical values are at respective nominal VDD. (2) 10000 cycles. (3) Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (measured at Y2), 4-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (manured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz, Y8/9 = 48 MHz. (4) The tsk(o) specification is only valid for equal loading of each bank of outputs and outputs are generated from the same divider; data sampled on rising edge (tr). (5) odc depends on output rise- and fall-time (tr/tf). 6 Submit Documentation Feedback |
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