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TDA8790M Datasheet(PDF) 9 Page - NXP Semiconductors |
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TDA8790M Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 20 page 1996 Feb 21 9 Philips Semiconductors Product specification 8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter TDA8790 3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 255 respectively) are connected to pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3. a) The current flowing into the resistor ladder is and the full-scale input range at the converter, to cover code 0 to code 255, is b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio will be kept reasonably constant from part to part. Consequently variation of the output codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 4. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, nor any significant attenuation is observed in the reconstructed signal. 5. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 6. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 7. Measurement carried out using video analyser VM700A, where video analog signal is reconstructed through a DAC. 8. Output data acquisition: the output data is available after the maximum delay time of td. I L V RT V RB – R OB R L R OT ++ ------------------------------------------ = V i R L I L × R L R OB R L R OT ++ ------------------------------------------ == V RT V RB ) – 0.838 V RT V RB – ( × = () × R L R OB R L R OT ++ ------------------------------------------ Fig.3 Explanation of note 3. handbook, halfpage RLAD ROT VRT VRM VRB ROB code 255 code 0 7 6 9 MGD284 IL RL |
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