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AM29240EH Datasheet(PDF) 9 Page - Advanced Micro Devices |
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AM29240EH Datasheet(HTML) 9 Page - Advanced Micro Devices |
9 / 36 page P R E L I M I N A R Y 9 Am29240 EH Microcontroller Series ™ Software debugging is facilitated by the instruction trace facility and instruction breakpoints. Instruction tracing is accomplished by forcing the processor to trap after each instruction has been executed. Instruction breakpoints are implemented by the HALT instruction or by a software trap. The processor provides several additional features to assist system debugging and testing: The Test/Development Interface is composed of a group of pins that indicate the state of the processor and control the operation of the processor. A Traceable Cache feature permits a hardware- development system to track accesses to the on- chip caches, permitting a high level of visibility into processor operation. An IEEE Std 1149.1-1990 (JTAG) compliant Stan- dard Test Access Port and Boundary-Scan Architec- ture. The Test Access Port provides a scan interface for testing processor and system hardware in a pro- duction environment, and contains extensions that allow a hardware-development system to control and observe the processor without interposing hard- ware between the processor and system. PERFORMANCE OVERVIEW The Am29240EH microcontroller series offers a signifi- cant margin of performance over CISC microprocessors in existing embedded designs, since the majority of pro- cessor features were defined for the maximum achiev- able performance at very low cost. This section describes the features of the Am29240EH microcontrol- ler series from the point of view of system performance. Instruction Timing The Am29240EH microcontroller series uses an arith- metic/logic unit, a field shift unit, and a prioritizer to execute most instructions. Each of these is organized to operate on 32-bit operands and provide a 32-bit result. All operations are performed in a single cycle. The performance degradation of load and store opera- tions is minimized in the Am29240EH microcontroller series by overlapping them with instruction execution, by taking advantage of pipelining, by an on-chip data cache, and by organizing the flow of external data into the processor so that the impact of external accesses is minimized. Pipelining Instruction operations are overlapped with instruction fetch, instruction decode and operand fetch, instruction execution, and result write-back to the Register File. Pipeline forwarding logic detects pipeline dependencies and routes data as required, avoiding delays that might arise from these dependencies. Pipeline interlocks are implemented by processor hardware. Except for a few special cases, it is not necessary to rearrange programs to avoid pipeline dependencies, although this is some- times desirable for performance. On-Chip Instruction and Data Caches On-chip instruction and data caches satisfy most proces- sor fetches without wait states. The caches are pipelined for best performance. The reload policies minimize the amount of time spent waiting for reload, while optimizing the benefit of locality of reference. Burst-Mode and Page-Mode Memories The Am29240EH microcontroller series directly sup- ports burst-mode memories. The burst-mode memory supplies instructions at the maximum bandwidth, with- out the complexity of an external cache or the perfor- mance degradation due to cache misses. The processor can also use the page-mode capability of common DRAMs to improve the access time in cases where page-mode accesses can be used. Instruction Set Overview All 29K family members employ a three-address instruc- tion set architecture. The compiler or assembly-lan- guage programmer is given complete freedom to allocate register usage. There are 192 general-purpose registers, allowing the retention of intermediate calcula- tions and avoiding needless data destruction. Instruc- tion operands may be contained in any of the general-purpose registers, and the results may be stored into any of the general-purpose registers. The Am29240EH microcontroller series instruction set contains 117 instructions that are divided into nine classes. These classes are integer arithmetic, compare, logical, shift, data movement, constant, floating point, branch, and miscellaneous. The floating-point instruc- tions are not executed directly, but are emulated by trap handlers. All directly implemented instructions are capable of executing in one processor cycle, with the exception of interrupt returns, loads, and stores. Data Formats The Am29240EH microcontroller series defines a word as 32 bits of data, a half-word as 16 bits, and a byte as 8 bits. The hardware provides direct support for word- integer (signed and unsigned), word-logical, word-Bool- ean, half-word integer (signed and unsigned), and char- acter data (signed and unsigned). Word-Boolean data is based on the value contained in the most significant bit of the word. The values TRUE and FALSE are represented by the most significant bit values 1 and 0, respectively. Other data formats, such as character strings, are sup- ported by instruction sequences. Floating-point formats |
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