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AM29243EH Datasheet(PDF) 11 Page - Advanced Micro Devices |
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AM29243EH Datasheet(HTML) 11 Page - Advanced Micro Devices |
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11 / 36 page  P R E L I M I N A R Y 11 Am29240 EH Microcontroller Series ™ channel at a time can use either DACKD, DACKC, DACKB, or DACKA, and the same channel uses the re- spective DREQD–DREQA signal for transfer requests. DMA transfers can occur to and from internal peripher- als independent of these acknowledgments. The DACKD and DACKC signals are supported on the Am29240EH and Am29243EH microcontrollers only. DREQD–DREQA DMA Request D through A (input, asynchronous, pull-up resistors) These inputs request an external transfer on a DMA channel. DMA requests are not dedicated to a particular channel—each channel specifies which request line, if any, it is using. Only one channel at a time can use either DREQD, DREQC, DREQB, or DREQA. This channel ac- knowledges a transfer using the respective DACKD– DACKA signal. These requests are individually program- mable to be either level- or edge-sensitive for either po- larity of level or edge. DMA transfers can occur to and from internal peripherals independent of these requests. The DMA request/acknowledge pairs DREQA/ DACKA and DREQB/ DACKB correspond to the Am29200 micro- controller signals DREQ0/DACK0 and DREQ1/DACK1, respectively. The pin placement reflects this correspon- dence, and a processor reset dedicates these request/ acknowledge pairs to DMA channels 0 and 1, respectively. This permits backward-compatible up- grade to an Am29200 microcontroller. The DREQD and DREQC signals are supported on the Am29240EH and Am29243EH microcontrollers only. DSRA Data Set Ready, Port A (output, synchronous) This indicates to the host that the serial port is ready to transmit or receive data on Serial Port A. DTRA Data Terminal Ready, Port A (input, asynchronous) This indicates to the processor that the host is ready to transmit or receive data on Serial Port A. GACK External Memory Grant Acknowledge (output, synchronous) This signal indicates to an external device that it has been granted an access to the processor’s ROM or DRAM, and that the device should provide an address. The processor can be placed into a slave configuration that allows tracing of a master processor. In this configu- ration, GACK is used to indicate that the processor pipe- line was held during the previous processor cycle. GREQ External Memory Grant Request (input, synchronous, pull-up resistor) This signal is used by an external device to request an access to the processor’s ROM or DRAM. To perform this access, the external device supplies an address to the ROM controller or DRAM controller. To support a hardware-development system, GREQ should be either tied High or held at a high-impedance state during a processor reset. ID31–ID0 Instruction/Data Bus (bidirectional, synchronous) The Instruction/Data Bus (ID Bus) transfers instructions to, and data to and from the processor. IDP3–IDP0 Instruction/Data Parity (bidirectional, synchronous) If parity checking is enabled by the PCE bit of the DRAM Control Register, IDP3–IDP0 are parity bits for the ID Bus during DRAM accesses. IDP3 is the parity bit for ID31–ID24, IDP2 is the parity bit for ID23–ID16, and so on. If parity is enabled, the processor drives IDP3–IDP0 with valid parity during DRAM writes, and expects IDP3–IDP0 to be driven with valid parity during DRAM reads. These signals are supported on the Am29243EH microcontroller only. INCLK Input Clock (input) This is an oscillator input at twice the system operating frequency. INTR3–INTR0 Interrupt Requests 3–0 (input, asynchronous, internal pull-up resistors) These inputs generate prioritized interrupt requests. The interrupt caused by INTR0 has the highest priority, and the interrupt caused by INTR3 has the lowest prior- ity. The interrupt requests are masked in prioritized or- der by the Interrupt Mask field in the Current Processor Status Register and are disabled by the DA and DI bits of the Current Processor Status Register. These signals have special hardening against metastable states, al- lowing them to be driven with slow-transition-time signals. LSYNC Line Synchronization (input, asynchronous) This signal indicates the start of a raster line. This signal is supported on the Am29240EH and Am29245EH mi- crocontrollers only. |
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