MAX109 datasheet(6/29 Pages) MAXIM

Part #	MAX109

Description	8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs

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Manufacturer	MAXIM [Maxim Integrated Products]

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6 / 29 page

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier

and 1:4 Demultiplexed LVDS Outputs

6

_______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.2Gsps, analog input

amplitude at -1dBFS differential, clock input amplitude 400mVP-P differential, digital output pins differential RL = 100Ω. Typical values

are at TA = +25°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SFDR300

fIN = 300MHz, fCLK = 2.2Gsps

61.7

SFDR1000

fIN = 1000MHz, fCLK = 2.2Gsps (Note 8)

44.4

51.1

SFDR1600

fIN = 1600MHz, fCLK = 2.2Gsps (Note 8)

43.7

50.3

SFDR2500

fIN = 2500MHz, fCLK = 2.2Gsps

45.0

SFDR500

fIN = 500MHz, fCLK = 2.5Gsps

53.7

Spurious Free Dynamic Range

SFDR1600

fIN = 1600MHz, fCLK = 2.5Gsps

44.6

dBc

SINAD300

fIN = 300MHz, fCLK = 2.2Gsps

44.1

SINAD1000 fIN = 1000MHz, fCLK = 2.2Gsps (Note 8)

40.4

43.1

SINAD1600 fIN = 1600MHz, fCLK = 2.2Gsps (Note 8)

37.9

42.1

SINAD2500 fIN = 2500MHz, fCLK = 2.2Gsps

40.1

SINAD500

fIN = 500MHz, fCLK = 2.5Gsps

43.1

Signal-to-Noise-Plus-Distortion

Ratio

SINAD1600 fIN = 1600MHz, fCLK = 2.5Gsps

40.5

dB

Third-Order Intermodulation

IM3

fIN1 = 1590MHz, fIN2 = 1610MHz at -7dBFS

-60

dBc

Metastability Probability

10

-14

TIMING CHARACTERISTICS

Maximum Sample Rate

fCLK(MAX)

2.2

Gsps

Clock Pulse-Width Low

tPWL

tCLK = tPWL + tPWH (Note 8)

180

ps

Clock Pulse-Width High

tPWH

tCLK = tPWL + tPWH (Note 8)

180

ps

Aperture Delay

tAD

200

ps

Aperture Jitter

tAJ

0.2

ps

Reset Input Data Setup Time

tSU

(Note 8)

300

ps

Reset Input Data Hold Time

tHD

(Note 8)

250

ps

tPD1

DCO = fCLK / 4, CLK fall to DCO rise time

1.6

tPD1DDR

DCO = fCLK / 8, DDR mode, CLK fall to

DCO rise time

1.6

CLK-to-DCO Propagation Delay

tPD1QDR

DCO = fCLK / 16, QDR mode, CLK fall to

DCO rise time

1.6

ns

tPD2

DCO = fCLK / 4, DCO rise to data transition

(Note 8)

-520

+520

tPD2DDR

DCO = fCLK / 8, DDR mode, DCO rise to

data transition (Note 8)

-520 +

2tCLK

520 +

2tCLK

DCO-to-Data Propagation Delay

tPD2QDR

DCO = fCLK / 16, QDR mode, DCO rise to

data transition (Note 8)

-520 +

2tCLK

520 +

2tCLK

ps

DCO Duty Cycle

Clock mode independent

45 to

55

%

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