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TDA9809 Datasheet(PDF) 6 Page - NXP Semiconductors |
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TDA9809 Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 40 page 1998 Jan 08 6 Philips Semiconductors Preliminary specification Single standard multimedia IF-PLL and FM radio demodulator TDA9809M Frequency Phased-Locked Loop detector (FPLL) The VIF amplifier output signal is fed, via a limiting amplifier, to a frequency and phase detector. During acquisition, the frequency detector generates a DC current that is proportional to the difference in frequency between the input signal and the VCO signal. After frequency lock-in, the phase detector generates a DC current proportional to the phase difference between the input signal and the VCO signal. The DC current generated by the frequency or phase detector is converted to a DC voltage via the loop filter, which controls the VCO frequency. VCO, TWD and TV AFC The VCO operates with a resonance circuit (with L and C in parallel) at double the Picture Carrier (PC) frequency. The VCO is controlled by two integrated variable capacitors. The control voltage required to tune the VCO from its free-running frequency to double the PC frequency is generated by the FPLL and fed via the loop filter to the first variable capacitor. This control voltage is amplified and converted into a current which represents the AFC output signal. At the centre frequency, the AFC output current is zero. The TWD divides the oscillator signal by 2 and generates two differential output signals with a 90 ° phase difference independent of frequency. Video demodulator and amplifier Video demodulation is realized by a multiplier designed for low distortion and wide bandwidth. The vision IF input signal and the ‘in-phase’ signal of the travelling wave divider output are multiplied together. The demodulated output signal is fed to the video amplifier via an integrated low-pass filter used to attenuate the carrier harmonics. This is an operational amplifier with internal feedback and wide bandwidth. A low-pass filter is integrated to attenuate the carrier harmonics. The video output signal at Vo(vid) is 1.1 V (p-p) for nominal vision IF modulation, in order to achieve 1 V (p-p) at the sound trap output. Intercarrier mixer The intercarrier mixer is realized by a multiplier. The sound IF signal passes through the vision IF SAW filter and the composite IF signal is then fed to the intercarrier mixer. Here, the IF signal is multiplied by the 90 ° TWD output signal to convert the sound IF to the intercarrier frequency. By using this quadrature detection, the low frequency video signals are removed. The mixer output signal is fed, via a high-pass filter used to attenuate the video signal components, at output pin 10. RIF amplifier and AGC detector The radio IF amplifier amplifies the 10.7 MHz radio IF signal. This signal is supplied by the tuner and is fed to the RIF input (pin 4) via a matching circuit and a ceramic band-pass filter. This amplifier contains two stages. The first stage, a conventional 0 dB differential amplifier designed for optimal dynamic range, is followed by a switchable differential amplifier stage with a gain of 10 dB. Either the radio IF or the TV IF signal can be selected at the output (pin 10). The RIF output signal is fed via ceramic band-pass filters to the FM-PLL demodulator and the radio IF AGC detector. The AGC threshold is very high and is designed to obtain some adjacent channel protection. The AGC detector output is fed to the tuner AGC output stage (pin 12) to control the tuner. FM-PLL demodulator, level detector and radio AFC The FM-PLL demodulator consists of a limiter and an FM phase-locked loop. The 8-stage internally AC-coupled limiter amplifies and limits the TV FM sound intercarrier or the radio FM intermediate frequency signal prior to demodulation. The limiter is designed for high sensitivity and AM suppression with low DC offset and needs no external pins for DC coupling. Furthermore, the AF output signal can be force muted by connecting a resistor between pin 11 and ground. The soft mute function can be disabled by connecting a resistor between pin 11 and the power supply. See the application circuit in Fig.16. |
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