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MAX16033LLB26+T Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX16033LLB26+T Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 21 page Low-Power Battery Backup Circuits in Small µDFN Packages 10 ______________________________________________________________________________________ Backup Battery Switchover To preserve the contents of the RAM in a brownout or power failure, the MAX16033–MAX16040 automatically switch to back up the battery installed at BATT when the following two conditions are met: 1) VCC falls below the reset threshold voltage. 2) VCC is below VBATT. Table 1 lists the status of the inputs and outputs in bat- tery-backup mode. The devices do not power-up if the only voltage source is VBATT. OUT only powers up from VCC at startup. Manual-Reset Input (MAX16033/MAX16037 Only) Many µP-based products require manual-reset capabil- ity, allowing the user or external logic circuitry to initiate a reset. For the MAX16033/MAX16037, a logic-low on MR asserts RESET. RESET remains asserted while MR is low and for a minimum of 140ms (tRP) after it returns high. MR has an internal 20kΩ (min) pullup resistor to VCC. This input can be driven from TTL/CMOS logic outputs or with open-drain/collector outputs. Connect a normally-open momentary switch from MR to GND to create a manual-reset function; external debounce cir- cuitry is not required. When driving MR from long cables or when using the device in a noisy environ- ment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. Watchdog Input (MAX16034/MAX16038 Only) The watchdog monitors µP activity through the watch- dog input (WDI). RESET asserts when the µP fails to toggle WDI. Connect WDI to a bus line or µP I/O line. A change of state (high to low, low to high, or a minimum 100ns pulse) resets the watchdog timer. If WDI remains high or low for longer than the watchdog timeout period (tWD), the internal watchdog timer runs out and triggers a reset pulse for the reset timeout period (tRP). The internal watchdog timer clears whenever reset is asserted or whenever WDI sees a rising or falling edge. If WDI remains in either a high or low state, a reset pulse periodically asserts after every watchdog timeout period (tWD); see Figure 2. Table 1. Input and Output Status in Battery-Backup Mode PIN STATUS VCC Disconnected from OUT OUT Connected to BATT BATT Connected to OUT. Current drawn from the battery is less than 1µA (at VBATT = 2.8V, excluding IOUT) when VCC = 0V. RESET Asserted BATTON High state MR, RESETIN, CEIN, and WDI Inputs ignored CEOUT Connected to OUT PFO Asserted tWD = WATCHDOG TIMEOUT PERIOD tRP = RESET TIMEOUT PERIOD WDI RESET tWD tWD tRP tRP Figure 2. MAX16034/MAX16038 Watchdog Timeout Period and Reset Active Time |
Similar Part No. - MAX16033LLB26+T |
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