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MAX16035PLB26+T Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX16035PLB26+T Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 21 page Low-Power Battery Backup Circuits in Small µDFN Packages _______________________________________________________________________________________ 9 Detailed Description The Typical Operating Circuit shows a typical connec- tion for the MAX16033–MAX16040. OUT powers the static random-access memory (SRAM). If VCC is greater than the reset threshold (VTH), or if VCC is lower than VTH but higher than VBATT, VCC is connected to OUT. If VCC is lower than VTH and VCC is less than VBATT, BATT is connected to OUT. OUT supplies up to 200mA from VCC. In battery-backup mode, an internal MOSFET connects the backup battery to OUT. The on- resistance of the MOSFET is a function of the backup- battery voltage and temperature and is shown in the BATT-to-OUT On-Resistance vs. Temperature graph in the Typical Operating Characteristics. Chip-Enable Signal Gating (MAX16033–MAX16036 Only) The MAX16033–MAX16036 provide internal gating of chip-enable (CE) signals to prevent erroneous data from being written to CMOS RAM in the event of a power failure or brownout condition. During normal operation, the CE gate is enabled and passes all CE transitions. When reset asserts, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The MAX16033–MAX16036 provide a series transmission gate from CEIN to CEOUT. A 2ns (typ) propagation delay from CEIN to CEOUT allows these devices to be used with most µPs and high- speed DSPs. When RESET is deasserted, CEIN is connected to CEOUT through a low on-resistance transmission gate. If CEIN is high when RESET is asserted, CEOUT remains high regardless of any subsequent transitions on CEIN during the reset event. If CEIN is low when RESET is asserted, CEOUT is held low for 1µs to allow completion of the read/write opera- tion (Figure 1). After the 1µs delay expires, CEOUT goes high and stays high regardless of any subsequent transitions on CEIN during the reset event. When CEOUT is disconnected from CEIN, CEOUT is actively pulled up to OUT. The propagation delay through the chip-enable circuit- ry depends on both the source impedance of the drive to CEIN and the capacitive loading at CEOUT. The chip-enable propagation delay is specified from the 50% point of CEIN to the 50% point of CEOUT, using a 50Ω driver and 50pF load capacitance. Minimize the capacitive load at CEOUT and use a low output-imped- ance driver to minimize propagation delay. In high-impedance mode, the leakage current at CEIN is ±1µA (max) over temperature. In low-impedance mode, the impedance of CEIN appears as a 75Ω resis- tor in series with the load at CEOUT. VCC VTH tRD tRD tRP tRP CEIN CEOUT RESET PFO PFI > VPFI RESET-TO-CEOUT DELAY * * IF CEIN GOES HIGH BEFORE RESET ASSERTS, CEOUT GOES HIGH WITHOUT DELAY AS CEIN GOES HIGH. Figure 1. RESET and Chip-Enable Timing |
Similar Part No. - MAX16035PLB26+T |
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Similar Description - MAX16035PLB26+T |
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