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M36L0R7040T0ZAQF Datasheet(PDF) 4 Page - STMicroelectronics |
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M36L0R7040T0ZAQF Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 18 page M36L0R7040T0, M36L0R7040B0 4/18 SUMMARY DESCRIPTION The M36L0R7040T0 and M36L0R7040B0 com- bine two memory devices in a Multi-Chip Package: a 128-Mbit, Multiple Bank Flash memory, the M30L0R7000T0 or M30L0R7000B0, and a 16- Mbit PseudoSRAM, the M69AR024B. Recom- mended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8x10mm, 8x10 ball array, 0.8mm pitch) package. In addition to the standard version, the packages are also available in Lead-free version, in compli- ance with JEDEC Std J-STD-020B, the ST ECO- PACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free solder- ing processes. The memory is supplied with all the bits erased (set to ‘1’). Figure 2. Logic Diagram Table 1. Signal Names Note: 1. A22-A20 are not connected to the PSRAM component. AI08467 23 A0-A22 DQ0-DQ15 M36L0R7040T0 M36L0R7040B0 GF 16 WF RPF WPF E1P GP WP UBP LBP VSS VDDF VPPF VDDP WAITF LF KF VDDQ EF E2P A0-A22 (1) Address Inputs DQ0-DQ15 Common Data Input/Output VDDF Power Supply for Flash Memory VDDQ Flash Memory Power Supply for I/O Buffers VPPF Flash Optional Supply Voltage for Fast Program and Erase VSS Ground VDDP PSRAM Power Supply NC Not Connected Internally DU Do Not Use as Internally Connected Flash Memory Control Functions LF Latch Enable Input EF Chip Enable Input GF Output Enable Input WF Write Enable Input RPF Reset Input WPF Write Protect Input KF Burst Clock WAITF Wait Data in Burst Mode PSRAM Control Functions E1P Chip Enable Input GP Output Enable Input WP Write Enable Input E2P Power-down Input UBP Upper Byte Enable Input LBP Lower Byte Enable Input |
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