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W83194BR-911 Datasheet(PDF) 11 Page - Winbond

Part # W83194BR-911
Description  STEPLESS VIA PT/PM MAIN CLOCK GENERATOR
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W83194BR-911 Datasheet(HTML) 11 Page - Winbond

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STEPLESS CLOCK FOR VIA PT/PM CHIPSET
Publication Release Date: March 2006
- 7 -
Revision 0.71
W83194BR-911, W83194BG-911
7. I2C CONTROL AND STATUS REGISTERS
7.1 Register 0: Frequency Select (Default = 10h)
BIT
NAME
PWD
DESCRIPTION
7
SSEL [4]
0
6
SSEL [3]
0
5
SSEL [2]
0
4
SSEL [1]
1
3
SSEL [0]
0
Frequency selection by software via I
2C
2
EN_SSEL
0
Enable software program FS [4:0].
0 = Select frequency by hardware.
1= Select frequency by software I
2C - Bit 7~ 3.
1
EN_SPSP
0 Enable Spread Spectrum in the frequency table.
0 = Normal
1 = Spread Spectrum enabled
0
EN_SAFE_FREQ
0 Enable reload safe frequency when the watchdog is timeout.
0 = reload the FS [4:0] latched pins when watchdog time out.
1 = reload the safe frequency bit defined at Register 5 bit 4~0.
7.2 Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: E2h)
BIT
PIN NO
PWD
DESCRIPTION
7
-
1
Reserved
6
43,42
1
CPUCLKT1 / C1 output control
5
40,39
1
CPUCLKT0 / C0 output control
4
-
X
Power on latched value of FS4 pin. Default: 0 (Read only)
3
-
X
Power on latched value of FS3 pin. Default: 0 (Read only)
2
-
X
Power on latched value of FS2 pin. Default: 0 (Read only)
1
-
X
Power on latched value of FS1 pin. Default: 1 (Read only)
0
-
X
Power on latched value of FS0 pin. Default: 0 (Read only)
7.3 Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh)
BIT
PIN NO
PWD
DESCRIPTION
7
10
1
PCI_F2 output control
6
9
1
PCI_F1 output control
5
8
1
PCI_F0 output control
4
Reserve
1
Reserved


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