21-Bit Deserializers with Programmable

Spread Spectrum and DC Balance

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11

Pin Description

PIN

NAME

FUNCTION

1

RxOUT17

2

RxOUT18

Channel 2 Single-Ended Outputs

3, 25, 32,

38, 44

GND

Ground

4

RxOUT19

5

RxOUT20

Channel 2 Single-Ended Outputs

6

SSG

Three-Level-Logic, Spread-Spectrum Generator Control Input. SSG selects the frequency spread of

RxCLKOUT relative to RxCLKIN (see Table 3).

7

DCB

Three-Level-Logic, DC-Balance Control Input. DCB selects DC-balanced, non-DC-balanced, or reserved

operation (see Table 1).

8

RxIN0-

Inverting Channel 0 LVDS Serial-Data Input

9

RxIN0+

Noninverting Channel 0 LVDS Serial-Data Input

10

RxIN1-

Inverting Channel 1 LVDS Serial-Data Input

11

RxIN1+

Noninverting Channel 1 LVDS Serial-Data Input

12

the pin as possible.

13, 18

LVDSGND

LVDS Ground

14

RxIN2-

Inverting Channel 2 LVDS Serial-Data Input

15

RxIN2+

Noninverting Channel 2 LVDS Serial-Data Input

16

RxCLKIN-

Inverting LVDS Parallel-Rate Clock Input

17

RxCLKIN+

Noninverting LVDS Parallel-Rate Clock Input

19, 21

PLLGND

PLL Ground

20

the pin as possible.

22

PWRDWN

5V-Tolerant LVTTL/LVCMOS Power-Down Input.

PWRDWN is internally pulled down to GND. Outputs are

high impedance when

PWRDWN = low or open.

23

RxCLKOUT

Parallel-Rate Clock Single-Ended Output. The MAX9242 has a rising-edge strobe. The MAX9244/MAX9246/

MAX9254 have a falling-edge strobe.

24

RxOUT0

26

RxOUT1

27

RxOUT2

Channel 0 Single-Ended Outputs

28, 36, 48

close to the pin as possible.

29

RxOUT3

30

RxOUT4

31

RxOUT5

33

RxOUT6

Channel 0 Single-Ended Outputs