TLV320AIC14CDBTRG4 datasheet(4/63 Pages) TI

Part #	TLV320AIC14CDBTRG4

Description	LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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TLV320AIC12, TLV320AIC13

TLV320AIC14, TLV320AIC15

TLV320AIC12K, TLV320AIC14K

SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007

Terminal Functions

TERMINAL

NAME

AIC12/13/12K

AIC14/15/14K

AIC12K

AIC14K

I/O

DESCRIPTION

DBT

RHB

NO.

IOVSS

1

5

I

Digital I/O ground

IOVDD

2

6

I

Digital I/O power supply

Frame sync delayed output. The FSD output synchronizes a slave

device to the frame sync of the master device. FSD is applied to the

slave FS input and is the same duration as the master FS signal. This

FSD

3

7

O

pin must be pulled low if AIC1x is a stand-alone slave. It must be

pulled high if the AIC1x is a stand-alone master or the last slave in the

cascade.

Frame sync. When FS goes low, DIN begins receiving data bits and

FS

4

8

I/O

DOUT begins transmitting data bits. In master mode, FS is internally

generated. In slave mode, FS is externally generated.

Data output. DOUT transmits the ADC output bits and registers data,

DOUT

5

9

O

and is synchronized to SCLK and FS. Data is sent out at the rising

edge of SCLK. Outside data/control frame, DOUT is put in 3-state.

Data input. DIN receives the DAC input data and register data from the

DIN

6

10

I

external DSP (digital signal processor) and is synchronized to SCLK

and FS. Data is latched at the falling edge of SCLK.

Master/slave select input. When M/S is high, the device is the master,

M/S

7

11

I

and when low it is a slave.

Power down. When PWRDN is pulled low, the device goes into a

power-down mode, the serial interface is disabled, and most of the

high-speed clocks are disabled. However, all the register values are

PWRDN

8

12

I

sustained and the device resumes full-power operation without

reinitialization when PWRDN is pulled high again. PWRDN resets the

counters only and preserves the programmed register contents.

Inverting output of the DAC. OUTM1 is functionally identical with and

complementary to OUTP1. This differential output can drive a

OUTM1

9

13

O

maximum load of 600

Ω. This output can also be used alone for

single-ended operation.

Noninverting output of the DAC. This differential output can drive a

OUTP1

10

14

O

maximum load of 600

Ω. This output can also be used alone for

single-ended operation.

DRVDD

11

15

I

Analog power supply for the 16-

Ω drivers OUTP2 and OUTP3

DRVSS

12

17

I

Analog ground for the 16-

Ω drivers OUTP2 and OUTP3

Analog output number 2 from the 16-

Ω driver. This output can drive a

OUTP2

13

–

18

–

O

maximum load of 16

Ω, and also can be configured as either

single-ended output or differential output by the control register 6.

Programmable virtual ground for the output of OUTP2 and OUTP3

OUTMV

14

–

19

–

O

(see the Register Map).

Analog output number 3 from the 16-

Ω driver. This output can drive a

OUTP3

15

–

20

–

O

maximum load of 16

Ω, and also be configured as either single-ended

output or differential output by the control register 6.

AVSS

16

21

I

Analog ground

AVDD

17

22

I

Analog power supply

MICIN

18

23

I

MIC preamplifier input. It must be connected to AVSS if not used.

INP2

19

24

I

Noninverting analog input 2. It must be connected to AVSS if not used.

INM2

20

25

I

Inverting analog input 2. It must be connected to AVSS if not used.

Bias output voltage is software selectable between 1.35 V and 2.35 V.

BIAS

21

27

O

Its output current is 5 mA.

INM1

22

28

I

Inverting analog input 1. It must be connected to AVSS if not used.

INP1

23

29

I

Noninverting analog input 1. It must be connected to AVSS if not used.

Hardware reset. The reset function is provided to initialize all of the

RESET

24

30

I

internal registers to their default values. The serial port is configured to

the default state accordingly.

Master clock. MCLK derives the internal clocks of the sigma-delta

MCLK

25

31

I

analog interface circuit.

SCL

26

32

I

Programmable host port (I2C or S2C) clock input.

SDA

27

1

I/O

Programmable host port (I2C or S2C) data line.

4

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