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MT48H32M16LFCJ-8L Datasheet(PDF) 10 Page - Micron Technology |
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MT48H32M16LFCJ-8L Datasheet(HTML) 10 Page - Micron Technology |
10 / 73 page PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 10 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Ball Descriptions Ball Descriptions Table 3: VFBGA Ball Descriptions 54-Ball VFBGA 90-Ball VFBGA Symbol Type Description F2 J1 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. F3 J2 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power- down and SELF REFRESH operation (all banks idle), active power- down (row active in any bank), deep power-down (all banks idle), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. G9 J8 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. F7, F8, F9 J9, K7, K8 CAS#, RAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. E8, F1 K9, K1, F8, F2 DQM0–3, LDQM, UDQM Input Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. For the x16, LDQM corresponds to DQ0–DQ7 and HDQM corresponds to DQ8–DQ16. For the x32, DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23, and DQM3 corresponds to DQ24–DQ31. DQM0–3 (or LDQM and HDQM if x16) are considered same state when referenced as DQM. G7, G8 J7, H8 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1 become “don’t care” when registering an ALL BANK PRECHARGE (A10 HIGH). H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2, G1 G8, G9, F7, F3, G1, G2, G3, H1, H2, J3, G7, H9, H3 A0–A12 Input Address inputs: A0–A12 are sampled during the ACTIVE command (row-address A0–A12) and READ/WRITE command [column-address A0–A8 (x32); column-address A0–A9 (x16); with A10 defining auto precharge] to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1. The address inputs also provide the op-code during a LOAD MODE REGISTER command. – H7 A13/NC Input H7 is used for the LG, reduced page-size, option (see Table 1 on page 1); otherwise, leave as NC. |
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