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MT48H32M16LFCJ-8IT Datasheet(PDF) 6 Page - Micron Technology |
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MT48H32M16LFCJ-8IT Datasheet(HTML) 6 Page - Micron Technology |
6 / 73 page PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 6 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Functional Block Diagrams The 512Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto refresh mode is provided, along with a power-saving deep power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. Functional Block Diagrams Figure 2: 32 Meg x 16 SDRAM RAS# CAS# CLK CS# WE# CKE CONTROL LOGIC MODE REGISTER A0–A12, BA0, BA1 DQML, DQMH 1,024 (x16) 16,384 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS COLUMN DECODER BANK0 MEMORY ARRAY (8,192 x 1,024 x 16) BANK0 ROW- ADDRESS LATCH AND DECODER 8,192 SENSE AMPLIFIERS DQ0– DQ15 16 BANK1 BANK2 BANK3 13 10 2 2 2 2 EXT MODE REGISTER BA1 BA0 Bank 0 0 0 0 1 1 1 0 2 1 1 3 DATA OUTPUT REGISTER DATA INPUT REGISTER 16 16 15 10 13 13 13 ROW- ADDRESS MUX REFRESH COUNTER ADDRESS REGISTER BANK CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH |
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