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C8051F066 Datasheet(PDF) 11 Page - Silicon Laboratories |
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C8051F066 Datasheet(HTML) 11 Page - Silicon Laboratories |
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11 / 328 page  C8051F060/1/2/3/4/5/6/7 Rev. 1.2 11 Figure 7.14. ADC2LTL: ADC2 Less-Than Data Low Byte Register ......................... 98 Figure 7.15. ADC Window Compare Example: Right-Justified Single-Ended Data . 99 Figure 7.16. ADC Window Compare Example: Left-Justified Single-Ended Data.... 99 Figure 7.17. ADC Window Compare Example: Right-Justified Differential Data.... 100 Figure 7.18. ADC Window Compare Example: Left-Justified Differential Data ...... 100 8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) .................... 103 Figure 8.1. DAC Functional Block Diagram............................................................ 103 Figure 8.2. DAC0H: DAC0 High Byte Register ...................................................... 105 Figure 8.3. DAC0L: DAC0 Low Byte Register........................................................ 105 Figure 8.4. DAC0CN: DAC0 Control Register........................................................ 106 Figure 8.5. DAC1H: DAC1 High Byte Register ...................................................... 107 Figure 8.6. DAC1L: DAC1 Low Byte Register........................................................ 107 Figure 8.7. DAC1CN: DAC1 Control Register........................................................ 108 9. Voltage Reference 2 (C8051F060/2) .................................................................... 111 Figure 9.1. Voltage Reference Functional Block Diagram ..................................... 111 Figure 9.2. REF2CN: Reference Control Register 2 .............................................. 112 10. Voltage Reference 2 (C8051F061/3) ................................................................... 113 Figure 10.1. Voltage Reference Functional Block Diagram.................................... 113 Figure 10.2. REF2CN: Reference Control Register 2 ............................................ 114 11. Voltage Reference 2 (C8051F064/5/6/7) .............................................................. 115 Figure 11.1. Voltage Reference Functional Block Diagram.................................... 115 Figure 11.2. REF2CN: Reference Control Register 2 ............................................ 116 12. Comparators ......................................................................................................... 117 Figure 12.1. Comparator Functional Block Diagram .............................................. 117 Figure 12.2. Comparator Hysteresis Plot ............................................................... 118 Figure 12.3. CPTnCN: Comparator 0, 1, and 2 Control Register ........................... 120 Figure 12.4. CPTnMD: Comparator Mode Selection Register ............................... 121 13. CIP-51 Microcontroller ......................................................................................... 123 Figure 13.1. CIP-51 Block Diagram....................................................................... 124 Figure 13.2. Memory Map ...................................................................................... 130 Figure 13.3. SFR Page Stack................................................................................. 133 Figure 13.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5...... 134 Figure 13.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs . 135 Figure 13.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR.... 136 Figure 13.7. SFR Page Stack Upon Return From PCA Interrupt ........................... 137 Figure 13.8. SFR Page Stack Upon Return From ADC2 Window Interrupt ........... 138 Figure 13.9. SFRPGCN: SFR Page Control Register ............................................ 139 Figure 13.10. SFRPAGE: SFR Page Register ....................................................... 139 Figure 13.11. SFRNEXT: SFR Next Register......................................................... 140 Figure 13.12. SFRLAST: SFR Last Register.......................................................... 140 Figure 13.13. SP: Stack Pointer ............................................................................. 148 Figure 13.14. DPL: Data Pointer Low Byte............................................................. 148 Figure 13.15. DPH: Data Pointer High Byte ........................................................... 148 Figure 13.16. PSW: Program Status Word............................................................. 149 |
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