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9704-11 Datasheet(PDF) 2 Page - Peregrine Semiconductor Corp. |
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9704-11 Datasheet(HTML) 2 Page - Peregrine Semiconductor Corp. |
2 / 10 page Product Specification PE9704 Page 2 of 10 ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0083-03 │ UltraCMOS™ RFIC Solutions 11 12 13 14 15 16 17 10 9 8 7 6 54321 44 43 42 41 40 35 34 33 32 31 30 29 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 R 4 R 5 M 0 M 1 V DD V DD M 2 M 3 S_WR, M 4 DATA, M 5 GND GND N/C V DD D OUT V DD N/C GND PD_D PD_U V DD C EXT Table 1. Pin Descriptions Figure 2. Pin Configurations (Top View) 44-lead CQFJ Figure 3. Package Type Pin No. Pin Name Interface Mode Type Description 1 VDD Both (Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended. 2 R0 Direct Input R Counter bit0 3 R1 Direct Input R Counter bit1 4 R2 Direct Input R Counter bit2 5 R3 Direct Input R Counter bit3 6 GND Both (Note 1) Ground 7 R4 Direct Input R Counter bit4 8 R5 Direct Input R Counter bit5 (MSB) 9 M0 Direct Input M Counter bit0 10 M1 Direct Input M Counter bit1 11 VDD Both (Note 1) Same as pin 1 12 VDD Both (Note 1) Same as pin 1 13 M2 Direct Input M Counter bit2 14 M3 Direct Input M Counter bit3 15 S_WR Serial Input Frequency register load enable input. Buffered data is transferred to the frequency register on S_WR rising edge. M4 Direct Input M Counter bit4 16 DATA Serial Input Binary serial data input. Data is entered LSB first, and is clocked serially into the 20-bit frequency control register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of CLOCK. M5 Direct Input M Counter bit5 |
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