1
Commercial/Industrial
04-02-037D
PEEL™ 22LV10AZ-25 / I-35
CMOS Programmable Electrically Erasable Logic Device
Features
•
Low Voltage, Ultra Low Power Operation
- Vcc = 2.7 to 3.6 V
- Icc = 5 µA (typical) at standby
- Icc = 1.5 mA (typical) at 1 MHz
- Meets JEDEC LV Interface Spec (JESD8-B)
- 5 Volt tolerant inputs and I/O’s
•
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
•
Application Versatility
- Replaces random logic
- Super set of standard PLDs
- Pin and JEDEC compatible with 22V10
- Ideal for battery powered systems
- Replaces expensive oscillators
•
Architectural Flexibility
- Enhanced architecture fits in more logic
- 133 product terms x 44 input AND array
- 12 inputs and 10 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear, synchronous preset
- Independent output enables
- Programmable clock; pin 1 or p-term
- Programmable clock polarity
- 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC
- Schmitt triggers on clock and data inputs
•
Schmitt Trigger Inputs
- Eliminates external Schmitt trigger devices
- Ideal for encoder designs
General Description
The PEEL22LV10AZ is a Programmable Electrically
Erasable Logic (PEEL) SPLD (Simple Programmable
Logic Device) that operates over the supply voltage
range of 2.7V-3.6V and features ultra-low, automatic
"zero" power-down operation. The PEEL22LV10AZ is
logically
and
functionally
similar
to
ICT's
5V
PEEL22CV10A and PEEL22CV10AZ. The "zero power"
(25
µA max. I
CC)
power-down mode makes the
PEEL22LV10AZ ideal for a broad range of battery-
powered portable equipment applications, from hand-
held
meters
to
PCMCIA
modems.
EE-
reprogrammability provides both the convenience of
product fast reprogramming for product development
and quick personalization in manufacturing, including
Engineering Change Orders.
The differences between the PEEL22LV10AZ and
PEEL22CV10A include the addition of programmable
clock polarity, p-term clock, and Schmitt trigger input
buffers on all inputs, including the clock. Schmitt trigger
inputs allow direct input of slow signals such as
biomedical
and
sine
waves
or
clocks.
Like
the
PEEL22CV10A, the PEEL22LV10AZ is a pin and
JEDEC compatible, logical superset of the industry
standard
PAL22V10
SPLD
Figure
1.
The
PEEL22LV10AZ
provides
additional
architectural
features that allow more logic to be incorporated into
the design. The PEEL22LV10AZ architecture allows it
to replace over twenty standard 24-pin DIP, SOIC,
TSSOP
and
PLCC
packages.
Figure 1 - Pin Configuration
I
VC C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/C LK
I
I
I
I
I
I
I
I
I
I
GN D
1
2
3
4
5
12
11
10
9
6
8
7
24
23
22
21
20
19
18
17
16
15
14
13
DIP
I/C LK
I
I
I
I
I
I
I
I
I
I
GN D
1
2
3
4
5
12
11
10
9
6
8
7
I
VC C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TSSOP
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
12
11
10
9
6
8
7
I
VC C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/C LK
I
I
I
I
I
I
I
I
I
I
GN D
24
23
22
21
20
19
18
17
16
15
14
13
SOIC
PLCC
I
I
I
I
I
I
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
5
6
7
8
9
10
11
2
4
26
28 27
1
3
24
23
22
21
20
19
25
18
17
16
14
13
12
15
Figure 2 - Block Diagram
PE EL
TM
"AND"
ARRAY
133 T erms
X
44 Inp uts
SP
AC
OE
MA CRO
CEL L
I/C LK
I
I
I
I
I
I
I
I
I
I
I
I/O
SP = SY NCHRONO US PR ES ET
AC = ASY NCHRONO US CLEA R
OE = OU TP U T EN AB LE
C LK MU X (O ptiona l)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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