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COP8SBE9 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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COP8SBE9 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 70 page  DC Electrical Characteristics (−40˚C ≤ T A ≤ +125˚C) (Continued) Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Conditions Min Typ Max Units RAM Retention Voltage, V R (in HALT Mode) 2.0 V Input Capacitance 7pF Voltage on G6 to Force Execution from Boot ROM(Note 8) G6 rise time must be slower than 100 ns 2xV CC V CC +7 V G6 Rise Time to Force Execution from Boot ROM 100 nS Input Current on G6 when Input > V CC V IN =11V,VCC = 5.5V 500 µA AC Electrical Characteristics (−40˚C ≤ T A ≤ +125˚C) Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Conditions Min Typ Max Units Instruction Cycle Time (t C) Crystal/Resonator 4.5V ≤ V CC ≤ 5.5V 0.5 DC µs Output Propagation Delay R L =2.2k, CL = 100 pF Frequency of MICROWIRE/PLUS in Slave Mode 2 MHz MICROWIRE/PLUS Setup Time (t UWS)20 ns MICROWIRE/PLUS Hold Time (t UWH)20 ns MICROWIRE/PLUS Output Propagation Delay (t UPD) 150 ns Input Pulse Width Interrupt Input High Time 1 t C Interrupt Input Low Time 1 t C Timer 1 Input High Time 1 t C Timer 1 Input Low Time 1 t C Timer 2, 3 Input High Time (Note 6) 1 MCLK or t C Timer 2, 3 Input Low Time (Note 6) 1 MCLK or t C Output Pulse Width Timer 2, 3 Output High Time 150 ns Timer 2, 3 Output Low Time 150 ns USART Bit Time when using External CKX 6 CKI periods USART CKX Frequency when being Driven by Internal Baud Rate Generator 2 MHz Reset Pulse Width 0.5 t C tC = instruction cycle time. Note 9: Maximum rate of voltage change must be < 0.5 V/ms. Note 10: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC and outputs driven low but not connected to a load. Note 11: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F, G0, and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to VCC; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Note 12: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins must be limited to < (VCC +7V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients. Note 13: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC. Note 14: Absolute Maximum Ratings should not be exceeded. Note 15: Vcc must be valid and stable before G6 is raised to a high voltage. www.national.com 11 |
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Similar Description - COP8SBE9 |
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