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DS3105 Datasheet(PDF) 9 Page - Maxim Integrated Products |
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DS3105 Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 110 page Preliminary. Subject to Change Without Notice. DS3105 Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. 9 of 110 5 DETAILED FEATURES Input Clock Features • Five input clocks: Three CMOS/TTL (≤125 MHz) and two LVDS/LVPECL/CMOS/TTL (≤156.25 MHz) • CMOS/TTL Input clocks accept any multiple of 2kHz up to 125MHz • LVDS/LVPECL inputs accept any multiple of 2kHz up to 131.072MHz, any multiple of 8kHz up to 155.52MHz plus 156.25 MHz • All input clocks are constantly monitored by programmable activity monitors • Fast activity monitor can disqualify the selected reference after two missing clock cycles • Three optional 2/4/8 kHz frame sync inputs for frame sync signals from master and slave timing cards and an optional backup timing source T0 DPLL Features • High-resolution DPLL plus three low-jitter output APLLs • Sophisticated state machine automatically transitions between free-run, locked and holdover states • Revertive or non-revertive reference selection algorithm • Programmable bandwidth from 18 Hz to 400 Hz • Separately configurable acquisition bandwidth and locked bandwidth • Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10 or 20 • Multiple phase detectors: phase/frequency, early/late, and multi-cycle • Phase/frequency locking ( ±360° capture) or nearest-edge phase locking (±180° capture) • Multi-cycle phase detection and locking (up to ±8191 UI) improves jitter tolerance and lock time • Phase build-out in response to reference switching • Less than 5 ns output clock phase transient during phase build-out • Output phase adjustment up to ±200 ns in 6 ps steps with respect to selected input reference • High-resolution frequency and phase measurement • Holdover frequency averaging over 1 second interval • Fast detection of input clock failure and transition to holdover mode • Low-jitter frame sync (8 kHz) and multi-frame sync (2 kHz) aligned with output clocks T4 DPLL Features • High-resolution DPLL can be used to monitor inputs • Programmable bandwidth from 18 Hz to 70 Hz • Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10 or 20 • Multiple phase detectors: phase/frequency, early/late, and multi-cycle • Phase/frequency locking ( ±360° capture) or nearest-edge phase locking (±180° capture) • Multi-cycle phase detection and locking (up to ±8191 UI) improves jitter tolerance and lock time • Phase detector can be used to measure phase difference between two input clocks • High-resolution frequency and phase measurement Output APLL Features • Three separate clock-multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates, Fast/Gigabit Ethernet rates and 10G Ethernet rates, all locked to a common reference clock • The T0 APLL, has frequency options suitable for Nx19.44MHz, NxDS1, NxE1, Nx25MHz and Nx62.5MHz • The T4 APLL has frequency options suitable for Nx19.44MHz, NxDS1, NxE1, NxDS2, DS3, E3, Nx10MHz, Nx10.24 MHz, Nx13MHz, Nx25 MHz and Nx62.5 MHz • The T0 APLL2 produces 312.5 MHz for 10G Synchronous Ethernet applications Output Clock Features • Two output clocks: one CMOS/TTL (≤125 MHz) and one LVDS/LVPECL (≤312.50 MHz) • Output clock rates include 2 kHz, 8 kHz, NxDS1, NxE1, DS2, DS3, E3, 6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz, 2.5 MHz, 25 MHz, 125 MHz, 156.25 MHz, 312.50 MHz, 10 MHz, 10.24 MHz, 13 MHz, 30.72 MHz and various multiples and submultiples of these rates • Custom clock rates also available: any multiple of 2 kHz up to 77.76 MHz and any multiple of 8 kHz up to 311.04MHz • All outputs have < 1 ns peak-to-peak output jitter; outputs from APLLs have < 0.5 ns peak-to-peak |
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